Full Description

Who we are

Persimmons is building the infrastructure that will power the next decade of AI. Founded in 2023 by veteran technologists from the worlds of semiconductors, AI systems, and software innovation, We're on a mission to enable smarter devices, more sustainable data centers, and entirely new applications the world hasn't imagined yet.

Why join us

We're growing fast and looking for bold thinkers, builders, and curious problem-solvers who want to push the limits of AI hardware and software. If you're ready to join a world-class team and play a critical role in making a global impact - we want to talk to you.

What you'll do

As a Senior ASIC Design Verification Engineer, you will be responsible for verifying critical blocks in the Persimmons inference chiplet that will run the smallest to largest AI models. Your primary duties and responsibilities include

Lead comprehensive verification planning and execution for fabric-level and full-chip designs, ensuring robust validation across all design hierarchies Collaborate cross-functionally with architecture, firmware, and design teams to develop detailed test plans that validate implementation against specifications and requirements Design and implement advanced testbenches featuring constrained random stimulus generation, intelligent checkers, comprehensive scoreboards, and targeted assertions to ensure design correctness and coverage Architect and execute verification strategies encompassing test planning, coverage analysis, automated regression management, and data-driven insights to maximize verification efficiency and quality Drive verification excellence through established methodologies including structured code reviews, agile sprint planning, and systematic feature deployment processes Innovate verification approaches by researching and implementing next-generation methodologies, automated flows, and emerging technologies including AI-driven verification tools

Requirements

What You Bring To The Table

Educational Foundation: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related technical discipline

Proven Experience: 7-10+ years of hands-on verification experience spanning test plan development, simulation environment creation, test implementation, and complex debugging across diverse IP blocks, SoCs, and system-level designs

Specialized Expertise: Demonstrated proficiency in fabric-level and chip-level verification methodologies and best practices

Technical Mastery: Advanced skills in SystemVerilog/Verilog, UVM methodology, and C/C++ programming, including embedded code development and validation for RISC-based processors

Verification Leadership: Established track record in creating scalable verification flows, implementing coverage-driven verification strategies, and developing assertion-based verification frameworks