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Infineon Technologies • India
Role & seniority: Senior Verification Engineer (8+ years in digital verification) at Infineon.
SystemVerilog, UVM
IP, subsystem, and SoC verification
RTL/GLS verification, low-power (UPF) and gate-level
Assertion-based and formal verification
Coverage-driven and constrained-random verification
Emulation-based verification (experience preferred)
Verification architecture design; verification planning and tracking
Define, coordinate, and implement verification concepts and overall verification strategy for complex SoCs
Develop advanced test benches and verification environments; lead test planning, execution, and coverage closure
Ensure work-process compliance and high-quality verification sign-off; manage verification planning, tracking, and reporting
8+ years in advanced SystemVerilog and UVM for IP/SoC verification
Experience with RTL/GLS verification and low-power design (UPF)
Proficiency in coverage-driven, constrained-random, and assertion-based testing
Formal verification experience
Ability to lead a team and develop verification architectures; test plan creation and execution
Exposure to automation methods and formal verification methodologies
Experience with emulation-based verification
SoC verification across RTL, Power Aware, and gate-level simulations
Candidate should have strong background in digital verification to develop advanced test benches using System Verilog and UVM.
Your Role
Key responsibilities in your new role
Candidate should have strong background in digital verification to develop advanced test benches using System Verilog and UVM. Should have developed multiple verification environments for complex IP’s and SoC’s by defining new architecture. Having knowledge in SoC verification covering RTL, Power Aware and Gate level simulations is preferable. Exposure to deployment of automation methods and formal verification methodologists preferable. Define and implement verification concepts for complex SoCs usingstate-of-the-art methodologies such metric driven, formal and emulation-based verification. Co-ordinate the overall verification strategy. Define and control verification management activities such as verification planning, verification tracking and reporting. Control for work process compliance and high-quality verification sign-off.
Your Profile
Qualifications And Skills To Help You Succeed
Bachelors/Masters in Electrical/Electronics Engineering with 8+ years of experience in Advanced user of System Verilog & UVM for IP , Subsystem, SOC level verification. Exposed to Coverage Driven & Constraint random Verification Experience with Assertion based & Formal Verification. Experience with low power design aspects , Power Aware Verification(UPF) and Gate level. Experience in verification of designs in RTL & GLS. Experience in developing verification architecture. Experience in leading a team, create & execute test plan, Coverageclosure
Shavin.Shashidhar@infineon.com
#WeAreIn for driving decarbonization and digitalization.
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