Role & seniority

Senior verification architect/lead role responsible for defining and implementing verification concepts for complex SoCs.

Stack/tools

SystemVerilog, UVM; SV/UVM-based testbench architecture
RTL, Power Aware and gate-level simulations
ARM-based SoC verification
HW/SW co-verification; automation and formal verification (plus)

Top 3 responsibilities

Define and implement verification concepts for complex SoCs using metric-driven, formal, emulation-based verification and HW/SW co-verification; define verification architecture for new IPs
Design architecture of advanced testbenches using SV/UVM; coordinate overall verification strategy
Define and control verification management activities (planning, tracking, reporting) and ensure process compliance and high-quality sign-off; implement power-aware and gate-level simulations

Must-have skills

MS with 12+ years or BS with 14+ years of experience
Strong background in digital verification using SystemVerilog and UVM
Proven track record developing multiple verification environments for complex IPs/SoCs
Experience defining verification architecture for new IPs and supervising verification environments
Worked on ARM-based SoC verification covering RTL, Power Aware, and gate-level simulations

Nice-to-haves

Exposure to automation and formal verification methodologies

Location & work type

Location: not specified

Work type: not specified

Full Description

In your new role you will

Define and implement verification concepts for complex SoCs usingstate-of-the-art methodologies such metric driven, formal andemulation-based verification as well as HW/SW co-verification
Design the architecture of advanced testbenches using SV/UVM
Co-ordinate the overall verification strategy
Define and control verification management activities such asverification planning, verification tracking and reporting
Control for work process compliance and high-quality verificationsign-off
Define and implement Power aware simulation and Gate levelsimulations

You are best equipped for this task if you have

MS with 12+ years / BS with 14+ years
Candidate should have strong background in digital verification usingSystem Verilog and UVM.
Should have developed multiple verificationenvironments for complex IP’s and SoC’s.
Should be capable ofdefining verification architecture for new IP’s and should havedeveloped verification environments.
Candidate should have worked on ARMbased SoC verification covering RTL, Power Aware and Gate levelsimulations.
Exposure to deployment of automation and formalverification methodologies is a plus.

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Principal Engineer Verification

Full Description

In your new role you will

You are best equipped for this task if you have