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Astera Labs • Israel
Role & seniority: Formal Verification Manager; leadership role establishing a new R&D center in Israel (full-time).
Stack/tools: Formal verification methodologies and environments; industry tools (e.g., Jasper, VC Formal or equivalents); RTL design and verification principles; SystemVerilog UVM-based verification (preferred); high-speed serial interfaces; networking standards (Ethernet, NVLink, UALink, PCIe) (contextual knowledge).
Build, mentor, and lead the Formal Verification team in Israel; own verification activities for the center.
Define verification methodologies, create environments from scratch, and drive sign-off readiness.
Collaborate with Architecture, Design, and DV teams; analyze results, debug issues, and advance formal techniques across projects.
Bachelor’s in Electrical Engineering or related field; 7+ years in formal verification at semiconductor companies.
Deep expertise in formal verification methods, tools, and flows; RTL design/verification knowledge.
Experience leading teams or projects; strong communication and results-oriented mindset; proficiency with standard formal tools (Jasper, VC Formal or equivalents).
Master’s degree; managerial experience in chip design/verification.
SystemVerilog UVM-based verification; knowledge of networking standards; background in high-speed serial interface verification.
Location & work type: Israel; full-time position
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Formal Verification Manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters. As the Formal Verification Manager, you will be a foundational member of our Israel R&D center, leading the formal verification activities that prove the correctness of complex connectivity designs. You won't just execute tasks—you will build and mentor a high-performing team, establish verification methodologies, and ensure our silicon meets rigorous correctness standards before tapeout. You will bridge Architecture, Design, and DV teams to identify verification needs and drive the adoption of advanced formal techniques that accelerate our time to market while maintaining the highest quality standards. Key Responsibilities Team Building & Leadership Build, mentor, and lead a high-performing Formal Verification team in Israel Own the formal verification activities across the R&D center Guide engineers in creating formal environments, analyzing complex designs, and applying advanced formal techniques Methodology & Strategy Development Define formal verification methodologies and strategies to prove correctness of designs Own and develop formal verification environments from scratch to sign-off Develop generic common formal functions for reuse across projects Cross-Functional Collaboration & Technical Excellence Work closely with Architecture, Design, and DV teams to identify verification needs and design requirements Analyze verification results, identify bugs, and collaborate with designers to resolve issues Drive adoption of formal verification techniques to complement traditional verification approaches Basic Qualifications Bachelor's degree in Electrical Engineering or related technical field 7+ years of hands-on experience in Formal Verification at semiconductor companies Deep expertise in formal verification methodologies, tools, and flows Proven experience leading teams or projects with excellent communication skills and a "can-do" approach Strong understanding of RTL design and verification principles Experience with industry-standard formal verification tools (Jasper, VC Formal, or similar) Preferred Qualifications Master's degree in Electrical Engineering or related field Managerial experience in chip design or verification domain Experience with SystemVerilog UVM-based design verification Knowledge of networking standards (Ethernet, NVLink, UALink, PCIe) Background in high-speed serial interface verification We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.