Full Description

Overall ownership of PCIe/LPDDR validation in Architecture, Pre-Silicon, Board Design, Post-Silicon activities, Proficiency in Debug Skills & Interoperability Interact with Architecture/Design/FW teams to identify actual FW implementation and plan/perform validation accordingly Review SoC Verification plan for PCIe/LPDDR sub system and Create/understand PCIe/LPDDR Validation plan with SOC C, AE, FW teams and architect/review/update C/FW based tests Develop understanding on SoC and perform Processor based SoC verification and Emulation using C/FW/AE Flow Should be able to run SOC C based simulations for test case understanding and debug using VCS Involve in Silicon Bring-up activity and support FW bring-up Work with overseas teams for PCIe/LPDDR bring-up/debug Bachelors/Masters in Engineering Thorough Knowledge of PCIe/LPDDR Standards is must. PCIe G5/G6 or LPDDR5 would be preferred. Experience with high‑speed serial protocols and SerDes PHY behavior Good understanding on PCIe / NVME Architecture or LPDDR architecture Minimum 14+ years of Processor based SoC, and hands-on PCIe validation experience with C/FW tests Hands on LA, PCIe Switches, PA, Exerciser set up (Viavi*, Lecroy), Hardware set up, Debug set up is A Must Good To Have - Knowledge of industry standard interfaces, such as ONFI, AXI is an advantage Good To Have - Debug, bring up experience with SNPS PCIe Controller, PHY is an advantage Proven experience in scripting languages such as Python / Perl / TCL Good written and oral communication Excellent Team Player, Positive attitude, well-mannered mature behavior is must