Role & seniority

PCIe Validation Engineer, mid-senior (5–8 years)

Stack / tools

PCIe Gen 4/5/6, CXL; RISC-V, ARM
Lab/test equipment: oscilloscopes, logic analyzers, BERTs, power analyzers
Languages: C/C++, Python, Perl
OS: Windows, Linux
Embedded firmware: bootloaders, PCIe drivers, test hooks

Top 3 responsibilities

Take lead in validating PCIe and subsystems across multiple SoC platforms; define and execute comprehensive test plans
Run tests for memory training, performance benchmarks, stress, timing margins, and overall reliability; perform root-cause analysis on failures
Collaborate with design and firmware teams to develop/integrate/debug firmware for PCIe training; write/adjust firmware components and enable testing; coordinate with board and SI/PI teams

Must-have skills

5–8 years total experience; ≥5 years SOC validation; ≥4 years post-silicon PCIe subsystem validation
Strong C/C++ programming for low-level code and hardware bring-up; experience integrating/debugging firmware in PCIe/SoC contexts
Deep PCIe knowledge (Physical/Data Link/Transaction layers), Gen 4/5/6, and CXL
Experience with silicon bring-up, PCIe protocol analyzers, oscilloscopes
Familiarity with embedded OS, boot sequences; system-level PCIe performance tuning; Linux and Windows

Nice-to-haves

RISC-V or ARM-based platforms experience
Experience generating firmware components (bootloaders, PCIe drivers) for training and bring-up
Scripting automation in Python/Perl; t

Full Description

Position: PCIe Validation Engineer

Exp: 5-8 years PCIe Gen 4/5/6, CXL, RISC-V, ARM, Oscilloscope, Multimeter, Logic & Power Analyzer, BERTS C/C++, Python, Perl, Windows, Linux Take lead responsibility for validating PCIe and its subsystems on multiple SoC platforms. Define comprehensive test plans and execute tests covering memory training procedures, performance benchmarks, stress scenarios, timing margin analysis, and overall reliability. Collaborate with design and firmware teams to develop, integrate, and debug firmware essential for PCIe training. Write necessary firmware components (like bootloaders, PCIe drivers, test hooks) to enable testing. Integrate and debug firmware for PCIe initialization and training, specifically on systems using RISC-V or ARM processors. Work closely with software and hardware teams to ensure firmware and hardware components interact correctly. Coordinate with board and Signal/Power Integrity (SI/PI) teams for related evaluations. Utilize standard lab equipment (oscilloscopes, logic analyzers, BERTs, power analyzers) for test execution, data collection, and troubleshooting memory-related issues. Perform root cause analysis for failures. Develop scripts (Python, Perl, C/C++) to automate test procedures and validation workflows. 5 to 8 years of experience 5+ years of SOC validation experience At least 4 years of experience in post-silicon PCIe subsystem validation Strong C/C++ programming skills, particularly for low-level code (like hardware abstraction layers) used in system bring-up. Proven experience integrating and debugging firmware in PCIe validation or general SoC environments. Deep understanding of PCIe protocols (Physical, Data Link, Transaction layers), PCIe Gen 4/5/6, and CXL Experience with silicon bring-up processes and Hands-on experience with PCIe protocol analyzers and oscilloscopes. Familiarity with embedded operating systems and the typical boot sequences. System-level PCIe performance tuning and characterization. Experience with Linux and Windows operating systems