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SiMa.ai • San Jose, California, United States
Salary: USD 220,000–296,400 per year
Role & seniority: Principal Engineer, PCIe Verification (senior individual contributor)
Location & work type: San Jose, CA; full-time, on-site
Stack/tools: PCIe Gen4/5; UVM + SystemVerilog; C/C++/Python; PCIe bring-up on silicon; emulation/test environments; exposure to UCIe protocols a plus
Define, develop, and verify PCIe test benches (UVM/SystemVerilog); lead code coverage reviews and functional coverage closure; develop SVA assertions
Bring up and test PCIe in block/full-chip environments; manage debug of test, regression, and emulation failures; execute test plans and performance measurements
Collaborate with Architecture, MLSoC Hardware, and MLA Software teams; bring up and debug PCIe in emulation and silicon; perform lab debug with software/systems teams as needed
BS/MS in EE or CS; 12+ years in functional verification and silicon bring-up/debug
Deep experience with UVM and SystemVerilog-based verification
Practical knowledge of PCIe Gen4/5; PCIe bring-up/debug on silicon
Strong debugging/problem-solving; good communication and teamwork
Experience with UCIe protocols
Proficiency in C/C++/Python
Prior work with emulation environments and PCie interface silicon debug
Additional notes: On-site presence required in San Jose, CA; role involves cross-functional collaboration with architecture, hardware, and software teams.
Description
Job Title: Principal Engineer, PCIe Verification
Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office)
Job ID: AI2441
The Design Verification (DV) engineer at SiMa is involved in the functional verification of PCIe controller and PCIe-phy at block, sub-system and MLSoC level. Will also be involved in PCIe bring-up and debug on emulator. Generate required PCIe controller and phy initialization (register programming code sequence) for PCIe bring up in Simulation, emulation and on silicon. Work on UCIe interface verification on next generation projects.
As the PCIe Design Verification Engineer, you will
Participate in PCIe architecture, micro-architecture, feature discussions and reviews. Define and develop PCIe test bench components using UVM & System Verilog. Bring up and testing of PCIe in block and full-chip test environment. Develop and execute a test plan. Verification execution of PCIe EP/RC functionality and performance measurements. Lead Code coverage reviews and closure. System Verilog Assertion functional coverage development and closure. Manage debug of test and regression failures, as well emulation failures. Work closely with the Architecture, MLSoC Hardware and MLA Software teams. Work with emulation and MLSoC Software team to bring up and debug PCIe. Work in the lab on PCie interface silicon debug with software and systems team as and when needed.
BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 12+ years of experience in functional verification and silicon bring-up/debug. Very good current working experience of UVM and System Verilog based verification methodology is a must. Working experience on PCIe protocols Gen4/5. Working experience on PCIe bring-up and debug on Silicon is a plus. Past working experience on UCIe protocols is a plus. Proficiency in C/C++/Python programming is a plus. Good debug and problem solving skill.
Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.
The annual salary for this position ranges from $220,000 - $296,400. The actual annual salary paid for this position will be based on several factors, including but not limited to, skills, prior experiences, qualifications, expertise, work location, total target compensation, training, company needs, and current market demands. The annual salary range for this position is subject to change and may be adjusted in the future.
EEO Employer: SiMa is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.