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European Tech Recruit • Amsterdam, North Holland, Netherlands
Role & seniority: ASIC Verification Engineer, senior/experienced level (≥5 years in ASIC verification)
Stack/tools: SystemVerilog, Verilog, UVM; digital design concepts; scripting (Python, Perl, or Tcl) is a plus
Develop and maintain UVM-based verification environments for complex digital designs
Create verification plans and test cases; implement/execute test benches to verify functionality, performance, and spec compliance
Debug issues, collaborate with design/architecture teams, drive verification methodology improvements, and mentor junior engineers
Must-have skills: Bachelor's or Master's in Electrical/Computer Engineering or related; ≥5 years ASIC verification; proficiency in SystemVerilog/Verilog and UVM; strong digital design and verification knowledge; problem-solving, communication, and teamwork
Nice-to-haves: Scripting experience (Python, Perl, Tcl); mentoring/leadership experience; experience with cross-functional collaboration and design reviews
Location & work type: Amsterdam, Netherlands; full-time role (on-site based in Amsterdam)
ASIC Verification Engineer
A fantastic opportunity for an experienced ASIC Verification Engineer to join a fast-scaling Semiconductor manufacturer based in Amsterdam, Netherlands.
Leveraging your extensive experience with Universal Verification Methodology (UVM) and verification techniques, you will contribute to the development of robust verification environments and methodologies. Collaborating closely with cross-functional teams including design, architecture, and software engineering to deliver high-quality solutions that meet or exceed customer expectations.
Responsibilities
Develop and maintain UVM-based verification environments for complex digital designs.
Create comprehensive verification plans and test cases based on design specifications.
Implement and execute test benches to verify functionality, performance, and compliance with specifications.
Debug issues and work closely with design engineers to resolve them in a timely manner.
Drive continuous improvement of verification methodologies, processes, and best practices.
Mentor junior team members and provide technical guidance as needed.
Collaborate with other teams to ensure alignment of verification efforts with project timelines and goals.
Participate in design reviews and contribute to architectural decisions from a verification perspective.
Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
Minimum of 5 years of experience in ASIC verification.
Proficiency in SystemVerilog, Verilog and UVM methodology.
Strong understanding of digital design concepts and verification techniques.
Excellent problem-solving skills and attention to detail.
Ability to work effectively both independently and as part of a team.
Excellent communication and interpersonal skills.
Experience with scripting languages such as Python, Perl, or Tcl is a plus.
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