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ALTEN India • Bengaluru, Karnataka, India
Role & seniority: Digital Verification Engineer, mid-senior level (4+ years)
SystemVerilog, UVM
Verification simulators: VCS, Questa, Xcelium
Debug: Verdi, SimVision, DVE
Scripting: Python, Perl, Shell, Tcl
Version control/regression: Git, Jenkins
Interfaces: AXI, AHB, DDR, PCIe, etc.
Develop and execute verification plans from design/specs; build SystemVerilog/UVM testbenches and reusable components
Create directed and constrained-random test cases; implement SystemVerilog Assertions; run/triage regression and close coverage gaps
Debug simulation failures with RTL designers; maintain testbench/documentation; automate workflows
Bachelor’s or Master’s in EE/CE or related field
4+ years in digital verification, with mixed-signal focus
Strong RTL/ digital logic knowledge (FSMs, pipelines, bus architectures)
Proficiency with SystemVerilog, UVM, and verification simulators
Experience with debug tools (Verdi/SimVision/DVE), coverage-driven verification
Familiarity with interfaces (AXI, AHB, DDR, PCIe); version control and regression systems
Knowledge of Formal Verification (JasperGold, VC Formal)
SoC-level verification, emulation, or FPGA prototyping
Low-power/UPF verification flows
Strong scripting for automation (Python, Perl, Shell, Tcl)
Location: Bengaluru
Work type: Full-time (on-site)
Join Our Team as a Digital Verification Engineer!
We are seeking a talented Digital Verification Engineer to join our dynamic team. As a key member of our verification team, you will play a crucial role in ensuring the functionality and reliability of our cutting-edge designs.
Location: Bengaluru
Key Responsibilities
Develop and execute verification plans based on design and architecture specifications. Build SystemVerilog/UVM-based testbenches and reusable verification components. Create directed and constrained-random testcases for functional and corner-case verification. Debug simulation failures using industry-standard tools and collaborate with RTL designers to resolve issues. Define, measure, and close functional and code coverage gaps. Implement SystemVerilog Assertions (SVA) for protocol and behavioral checking. Run and monitor regression suites; triage failing tests and track issues. Participate in specification reviews, design reviews, and verification progress meetings. Maintain clear documentation for testbench architecture, test scenarios, and verification results. Automate verification workflows using scripting languages such as Python, Perl, Shell, or Tcl.
Required Skills & Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. Strong understanding of digital logic, RTL design, FSMs, pipelines, and bus architectures. Hands-on experience with SystemVerilog and UVM methodology. 4+ years of experience in digital verification with a focus on mixed signal circuits and systems. Proficiency with verification simulators (e.g., VCS, Questa, Xcelium). Experience using debug tools such as Verdi, SimVision, or DVE. Familiarity with version control and regression systems (Git, Jenkins, etc.). Solid understanding of coverage-driven verification techniques. Experience verifying standard interfaces (AXI, AHB, DDR, PCIe, etc.). Strong analytical, debugging, and problem-solving skills.
Preferred Qualifications
Knowledge of Formal Verification methodologies and tools (e.g., JasperGold, VC Formal). Strong scripting experience for automation (Python, Perl, Shell, Tcl). Experience with SoC-level verification, emulation, or FPGA prototyping. Exposure to low-power/UPF verification flows.
Personal Attributes
Strong communication and teamwork abilities. Self-driven, with the ability to work independently in a fast-paced environment. Detail-oriented and committed to delivering high-quality results.
If you are passionate about verification and enjoy working in a collaborative environment, we would love to hear from you. Join us in shaping the future of digital verification!