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Tessolve • California, United States
Role & seniority
Stack/tools
SystemVerilog, UVM
Verification IPs (VIPs), testbench components (scoreboards, monitors, drivers)
Simulation: Synopsys VCS, Cadence Xcelium, Mentor Questa
Debug/trace: Verdi, DVE
Scripting: Python, Perl, TCL, Shell
SoC/digital interfaces knowledge
Top 3 responsibilities
Develop verification plans, scope, objectives, and coverage goals for IP/subsystem/SoC features
Architect and implement predictive UVM/SystemVerilog testbenches; build reusable DV components; run directed/constrained-random tests and regression suites
Analyze failures, perform root-cause debugging, drive coverage closure, and prepare sign-off documentation; collaborate across RTL, DFT, STA, firmware
Must-have skills
6+ years hands-on ASIC/IP design verification or related DV roles
Proficiency in SystemVerilog and UVM methodologies
Experience with simulation/verification tools (VCS, Xcelium, Questa)
Debugging, waveform analysis, issue reporting
Scripting for automation/regressions (Python, Perl, TCL, Shell)
Solid understanding of SoC architecture and digital interfaces
Nice-to-haves
Experience with high-speed interfaces (PCIe, USB, DDR/LPDDR, Ethernet, CXL)
Coverage-driven verification, metric analysis
Formal verification, low-power verification (UPF/CPF), or emulation
DFT concepts; collaboration with test teams
Global/multi-national team delivery experience
Location & work
About the Role
As a Design Verification Engineer at Tessolve, you will be part of the VLSI Design and Verification team working on verification of advanced ASIC/IP blocks and subsystem features. You’ll be responsible for building robust verification environments, executing feature-level and system-level tests, and ensuring design readiness for silicon tape-out and integration.
Key Responsibilities
Verification Planning & Strategy
Develop verification plans based on design specifications and requirements. Define verification scope, objectives, and coverage goals for IP/subsystem/SoC features.
Testbench and Methodology
Architect and implement predictive UVM/SystemVerilog testbenches. Build reusable verification components (scoreboards, monitors, drivers). Integrate Verification IP (VIPs) for complex protocol interfaces.
Test Development & Execution
Write directed and constrained-random test cases to validate functionality. Apply assertion-based verification (SVA) to capture functional checks. Run regressions and feature-driven scenarios for coverage closure.
Debug & Analysis
Analyze simulation failures using tools (e.g., Verdi, DVE). Debug design/testbench interactions and provide root-cause analysis.
Coverage & Sign-off
Report and drive functional/code/line coverage to closure. Ensure thorough documentation and participate in verification reviews.
Cross-Team Collaboration
Work closely with RTL design, DFT, STA, and firmware teams to align verification goals. Participate in Integration and Silicon Bring-up readiness activities.
Required Skills & Qualifications
Bachelor’s / Master’s in Electrical/Electronics/Computer Engineering or related field. 6+ years hands-on experience in ASIC/IP Design Verification or related DV roles. Proficiency with SystemVerilog and UVM methodologies. Experience with simulation & verification tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa). Strong debugging skills, waveform analysis, and issue reporting. Good scripting skills (Python, Perl, TCL, Shell) for automation and regressions. Solid understanding of SoC architecture and digital interfaces.
Preferred Expertise
Experience with high-speed interfaces (e.g., PCIe, USB, DDR/LPDDR, Ethernet, CXL). Familiarity with coverage-driven verification and metric analysis. Exposure to formal verification, low-power verification (UPF/CPF), or emulation. Knowledge of DFT concepts and collaboration with test teams. Experience working in multi-national teams with global delivery models.
What You’ll Gain
Opportunity to work on cutting-edge semiconductor designs in a global engineering team. Hands-on experience across the pre-silicon verification lifecycle from plan to sign-off. Exposure to advanced methodologies and tools used in modern DV flows.