Role & seniority: Senior ASIC/FPGA Verification Engineer (lead-level responsibilities possible)

Stack/tools: RTL verification with Siemens Mentor Graphics Questa or ModelSim; SystemVerilog + UVM/UVM-oriented testbenches; coverage, constrained-random, assertions; Register Abstraction Layer; scripting (Linux shell, TCL, Python); Formal Verification tools; CI (GitLab); familiarity with QVIP, AXI/PCIe/SpaceWire/Ethernet; FPGA/SoC debugging; HW/SW integration

Top 3 responsibilities

Define architecture, verification strategy, testbenches, and simulation plans for ASIC/FPGA designs
Develop/verify testbenches (UVM), run functional/coverage tests, analyze results, and improve processes
Collaborate across teams, review tools/vendors, and support HW/SW integration and verification milestones

Must-have skills

Bachelor’s in Electrical/Computer Engineering (or related field) with 5+ years of relevant experience, or Master’s with 3+ years
Proficient in SystemVerilog, UVM, and RTL simulation in Linux environments
Experience with coverage, constrained-random testing, assertions, andRegister Abstraction Layer
Scripting (Python, TCL, shell), debugging FPGA/ASIC issues, and strong communication

Nice-to-haves

Experience with Xilinx devices/IP, PCIe/AXI interfaces, DSP/components; QVIP familiarity
Formal verification, code coverage, waivers; GitLab CI; requirement tracing and verification strategy development
Embedded micro-processing systems kn

Full Description

Basic Qualifications Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree and 3 years of job-related experience.

Clearance Requirements

Department of Defense TS/SCI security clearance is preferred at time of hire. Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.
Responsibilities for this Position

Primary Job Qualifications

We encourage you to apply if you have any of these preferred skills or experiences

In-depth experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or equivalent in a Linux Environment
In-depth knowledge of System Verilog object oriented programming and the Universal Verification Methodology (UVM)
Understands UVM Testbench Architectures
Comfortable using and developing UVM agents, bus functional models
Understands different types of coverage, usage of cover classes, cover points, etc
Experience with predictive testbench components, functional coverage and assertions
Experience with constrained random testing
Experience with the Register Abstraction Layer
Familiarity with requirements-based verification, requirement tracing, and developing requirement verification strategies etc
Experience with scripting languages such as Linus shell scripts, TCL, Python
Familiarity with using Formal Verification tools, code coverage, writing waivers etc
Familiarity with the following are also helpful
Questa Verification IP (QVIP)
Developing UVM testbenches for designs implemented in Xilinx devices with Xilinx IP and SoCs
AXI protocols, PCIe, Space Wire, and Ethernet interfaces
DSP functions and common signal processing components
Familiar with debugging FPGA/ASIC hardware and assisting with HW/SW integration
Continuous Integration features of GITLab

Duties and Tasks: • Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments• Determines architecture, system simulation and detailed design approach• Defines module interfaces and all aspects of device design and simulation• Creates test and simulation plans that establish functional criteria• Verifies test results and analyzes performance• May also review vendor capabilities and simulation tools• Participates in the improvement of the ASIC/FPGA organizational processes• Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle• May provide leadership and/or direction to lower level employees• Independently determines approach to solutions• Contributes to the completion of major programs and projects• Plans and executes project tasks for activities described above

Advanced ASIC FPGA Verification Engineer