Full Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

SENIOR SILICON DESIGN ENGINEER

THE ROLE

• The focus of this role is to plan, develop, and execute the SoC verification of new and existing features for AMD’s ASIC and FPGA SoCs, ensuring there are no bugs in the final design.

THE PERSON

• You have a passion for next-generation FPGA and ASIC design verification. You are a team player with excellent communication skills and experience collaborating with engineers across different sites and time zones. You possess strong analytical and problem-solving abilities, and you're eager to learn and take on challenges.

KEY RESPONSIBILITIES

• Work as a member of a geographically distributed verification team to verify next-generation ASIC and FPGAs
• Develop testplans, implement testbenches, create testcases, and ensure functional coverage closure.
• Handle regression testing and contribute to verification infrastructure development.
• Develop both directed and random verification tests.
• Debug test failures, identify root causes, and work with RTL and firmware engineers to resolve design defects and test issues.
• Review functional and code coverage metrics, modify or add tests or constrain random tests to meet coverage requirement
• Collaborate with design , software and architecture teams to verify design under test.

PREFERRED EXPERIENCE

• Proficient in IP-level FPGA and ASIC verification.
• Knowledge of PCIe, CXL or other IO protocol is preferred
• Proficient in Verilog/SystemVerilog, and scripting languages such as Perl or Python.
• Hands-on experience with SystemVerilog and UVM is mandatory.
• Experience in developing UVM-based verification testbenches, processes, and flows.
• Solid understanding of design flow, verification methodology, and general computational logic design and verification

ACADEMIC CREDENTIALS

• Bachelor’s degree with 7+ years of experience, or Master’s degree with 5+ years of experience in Computer Engineering or Electrical Engineering.