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Platform Recruitment • London, England, United Kingdom
Role & seniority: Verification Engineer (mid-level to senior, FPGA/ASIC focus)
Stack/tools: FPGA/ASIC RTL, SystemVerilog, UVM, Python for verification tooling and automation, cocotb desirable; mixed open-source and proprietary verification environment; testbenches, CI pipelines, verification infrastructure
Design and maintain robust testbenches and targeted tests; develop and own verification plans with defensible coverage goals
Identify/diagnose RTL issues with designers to accelerate bring-up and defect resolution
Oversee and refine test infrastructure, including test suites, CI pipelines, and tooling improvements
2+ years professional RTL functional verification experience for FPGA or ASIC
Proficiency in SystemVerilog and UVM (stimulus development, coverage collection/analysis)
Strong debugging/analytical ability to isolate complex RTL/testbench issues
Python proficiency for verification infrastructure, tooling, and automation
Experience with cocotb
Location & work type: Location and work type not specified in source
We're working with one of the most prestigious high-frequency trading companies in the world to find a verification engineer to help verify their complex low-latency FPGA systems.
You'll be joining a team at the forefront of innovation in design verification, where you'll be supported in pushing the envelope alongside top pioneers in verification.
Responsibilities
Design and maintain robust testbenches and targeted tests using the organisation’s mixed open-source and proprietary verification environment. Develop and own comprehensive verification plans, ensuring coverage goals and test strategies are clear and defensible. Identify and diagnose RTL issues quickly, working directly with designers to accelerate bring-up and resolve design defects efficiently. Oversee and refine the test infrastructure, including management of test suites, CI pipelines, and the improvement of both internal and open-source tooling.
Requirements
Strong debugging and analytical capability, able to isolate and resolve complex RTL and testbench issues efficiently. Proficiency in Python for building verification infrastructure, tooling, and automation - beyond simple scripts. At least two years of professional RTL functional verification experience for FPGA or ASIC designs. Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis. Experience with cocotb desirable.
Apply below for more information!