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Platform Recruitment • Austin, Texas, United States
Role & seniority: Verification Engineer (mid–senior level) focusing on low-latency FPGA systems in high-frequency trading.
FPGA/ASIC RTL verification (SystemVerilog, UVM)
Testbench development with mixed open-source and proprietary tooling
Python for verification infrastructure, tooling, and automation
CI pipelines; test suites; exposure to cocotb desirable
Design and maintain robust testbenches and targeted tests within the mixed tool environment
Develop and own comprehensive verification plans with clear coverage goals and test strategies
Identify/diagnose RTL issues with designers to accelerate bring-up and resolve defects; oversee test infrastructure improvements
Strong debugging and analytical ability for RTL and testbench issues
Proficiency in Python for verification tooling and automation
Professional RTL functional verification experience for FPGA/ASIC
Hands-on SystemVerilog and UVM experience, including stimulus development and coverage analysis
Experience with cocotb
Familiarity with CI pipeline integration and open-source tooling
Open to working with open-source hardware tooling ecosystems
Location & work type: Location and work-type not specified; details to be provided by employer.
We're working with one of the most prestigious high-frequency trading companies in the world to find a verification engineer to help verify their complex low-latency FPGA systems.
You'll be joining a team at the forefront of innovation in design verification, where you'll be supported in pushing the envelope alongside pioneers in open-source hardware tools.
Responsibilities
Design and maintain robust testbenches and targeted tests using the organisation’s mixed open-source and proprietary verification environment. Develop and own comprehensive verification plans, ensuring coverage goals and test strategies are clear and defensible. Identify and diagnose RTL issues quickly, working directly with designers to accelerate bring-up and resolve design defects efficiently. Oversee and refine the test infrastructure, including management of test suites, CI pipelines, and the improvement of both internal and open-source tooling.
Requirements
Strong debugging and analytical capability, able to isolate and resolve complex RTL and testbench issues efficiently. Proficiency in Python for building verification infrastructure, tooling, and automation - beyond simple scripts. Professional RTL functional verification experience for FPGA or ASIC designs. Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis. Experience with cocotb desirable.
Apply below for more information!