Role & seniority: Senior RTL Verification Engineer (5–10 years in hardware verification)

Stack/tools: SystemVerilog; RTL testbenches; verification methodologies; EDA infrastructure; familiarity with UVM/Cocotb; optional: Python, Git, AXI/PCIe/Ethernet/DDR, FPGA prototyping, SystemC/C++

Top 3 responsibilities

Develop and maintain RTL testbenches, benchmarks, and supporting verification infrastructure
Drive verification methodology adoption across the team and onboard engineers
Collaborate with hardware, software, and ML teams to advance semiconductor design and AI-enabled solutions

Must-have skills

BS/MS in ECE, CE, or CS
5–10 years in hardware verification or related areas
Proficiency in SystemVerilog; experience writing test plans, building testbenches, and analyzing coverage
Strong communication and documentation abilities; able to operate in a fast-paced, startup-like environment

Nice-to-haves

Python scripting for automation
Version control workflows (Git)
Knowledge of AXI/PCIe/Ethernet/DDR; verification frameworks (UVM, Cocotb)
FPGA prototyping and debugging; SystemC/C++ high-level modeling
Location & work type: Redwood City, CA; on-site; full-time permanent; eligible US work authorization required (no C2C)

Full Description

We are seeking a Sr. RTL Verification Engineer to join our team in Redwood City to bring the power of generative AI to enhance and speed the design and manufacture of complex semiconductors.

Employment Type: Full-Time Permanent

Location: Redwoor City, CA (onsite)

Work Status: Work authorization in the U.S. (citizenship, permanent residency, or eligible work visa). No C2C.

What You'll Do

Collaborate with experts in hardware, software, and machine learning to develop advanced computing solutions at the intersection of semiconductor design and AI.
Develop and maintain RTL testbenches, benchmarks, and supporting EDA infrastructure.
Drive verification methodology adoption across the team and help onboard engineers from other domains to verification practices.

Requirements Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or Computer Science. 5–10 years of experience in hardware verification or related areas. Strong proficiency in SystemVerilog and verification methodology. Demonstrated experience writing test plans, building testbenches, and analyzing coverage. Strong communication and documentation skills. Comfortable working in a fast-paced, research-driven startup environment.

Nice to Have

Scripting/coding skills (Python preferred) for automation.
Familiarity with version control workflows (Git or similar).
Understanding of standard hardware interfaces and protocols (e.g., AXI, PCIe, Ethernet, DDR).
Hands-on experience with verification frameworks (UVM, Cocotb, or similar).
Exposure to FPGA prototyping and debugging.
Familiarity with high-level synthesis or modeling in SystemC / C++.

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