Full Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE

• As an IP verification engineer in the AECG Group, you will help bring to life cutting-edge FPGA, ASICs for variety of target customers. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success.

THE PERSON

• You have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBLITIES

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified for PCIe CXL based IP's
• Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
• Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers
• Build the directed and random verification tests
• Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality

PREFERRED EXPERIENCE

• Proficient in IP level ASIC verification is a must
• Experience with PCIe or CXL or ethernet protocols is a plus
• Expert in Verilog, System Verilog, Object Oriented programming
• Expertise in developing UVM based verification frameworks and testbenches
• Scripting and automation of verification processes and flows
• Exposure to leadership or mentorship is an asset
• Experience working in a team environment through the ASIC / FPGA Project lifecycle from Planning to Tape Out
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process