
DV Engineer / Senior Engineer – PCIE/CXL Subsystem Verification
Quest Global • Bengaluru, Karnataka, India
Role & seniority
- PCIE Gen6/CXL 3.0 IP/Subsystem Design Verification Engineer; senior verification profile (7+ years)
Stack/tools
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SystemVerilog/UVM, SOC/IP verification
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PCIE Gen6, CXL 3.0 verification
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Verification tools: VCS, Xcelium
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Scripting: Python, Perl
Top 3 responsibilities
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Develop and execute SystemVerilog/UVM testbenches for SOC/IP verification
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Create test plans, implement and run directed, constrained-random tests; debug failures
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Perform functional and code coverage analysis and drive sign-off through resolution with RTL team
Must-have skills
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7+ years of verification experience with hands-on SV/UVM
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Strong experience with PCIE Gen6 and CXL 3.0
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Proficiency with VCS/Xcelium and debugging environments
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Scripting competence (Python/Perl)
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Strong debugging, analytical, and problem-solving abilities
Nice-to-haves
- Experience mentoring and leading a team toward deliverables
Location & work type
- Location and work-type details not specified in the provided text; not disclosed.
Full Description
Job Requirements At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster. Key Responsibilities
- We are looking for passionate and motivated PCIE Gen6/CXL 3.0 IP/Subsystem Design Verification Engineers to work on PCIE/CXL based Memory Pooling application SOC.
- You will be part of a dynamic verification team contributing to pre-silicon verification using System Verilog & UVM
Key Responsibilities
- Develop and execute Systemverilog/UVM Testbenches for SOC/IP Verification
- Develop Test plan, Implement & run directed, random, and constrained random tests
- Debug simulation failures and work with RTL team for resolution.
- Functional & code coverage analysis and sign-off checklist closure.
Required Skills
- 7+ years of Verification experience with hands-on knowledge in SV/UVM
- Strong Working experience in PCIE Gen6/CXL3.0
- Familiarity with standard verification tools ( VCS, Xcelium) and debug environment
- Scripting skills ( Python/Perl)
- Strong debugging, analytical and problem-solving skills
Optional/Preferred Skills
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Experience in Mentoring & Driving team for towards deliverables.
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We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.
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We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.