Senior Design Verification Engineer
Silicon Patterns • Bengaluru, Karnataka, India
Role & seniority: Design Verification Engineer, mid–senior (5–12+ years)
Stack/tools: SystemVerilog, UVM; PCIe Gen 5 / Gen 6 (LTSSM, Equalization, Flow Control, AER, SR-IOV); CXL (CXL.io, CXL.cache, CXL.mem); verification IPs (VIPs); assertion-based verification (SVA); simulators (VCS, Questa, Xcelium); protocol analyzers
Top 3 responsibilities
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Develop and execute UVM-based verification environments for PCIe and CXL IPs (Gen 5/6)
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Verify PCIe/CXL protocol layers; create/test plans, coverage models, assertions, scoreboards; debug at protocol level
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Perform functional, regression, corner-case verification; collaborate with RTL/design teams; support SoC-level integration verification
Must-have skills
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Strong DV background with SystemVerilog and UVM
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Hands-on PCIe Gen 5/Gen 6 experience (LTSSM, Equalization, Flow Control, AER, SR-IOV)
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Good understanding of CXL (CXL.io, CXL.cache, CXL.mem) and VIPs for PCIe/CXL
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Proficiency in assertion-based verification (SVA) and strong debugging at block/SoC level
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Familiarity with simulation tools (VCS, Questa, Xcelium)
Nice-to-haves
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SoC-level integration experience; contributions to verification methodology improvements and automation beyond core DV
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Exposure to protocol analyzers and end-to-end interconnect verification workloads
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Location & work type: Bangalore; full-time role (notice period: immediate to 90 days)
Full Description
Job Description
Position: Design Verification Engineer – PCIe / CXL Gen 5 & Gen 6
Company: Silicon Patterns
Location: Bangalore
Experience: 5–12+ Years (can be adjusted)
Notice Period: Immediate to 90 Days
Role Overview Silicon Patterns is looking for a highly skilled Design Verification Engineer with strong expertise in PCIe and CXL protocols (Gen 5 & Gen 6). The role involves end-to-end verification of high-speed interconnect IPs and SoCs, working closely with design, architecture, and validation teams.
Key Responsibilities Develop and execute UVM-based verification environments for PCIe and CXL IPs (Gen 5 / Gen 6) Verify PCIe/CXL protocol layers (PHY, Link, Transaction layers) Create and maintain test plans, coverage models, assertions, and scoreboards Perform functional, regression, and corner-case verification Debug protocol-level issues using System Verilog, UVM, and protocol analyzers Collaborate with RTL designers to resolve functional and performance issues Support SoC-level integration verification involving PCIe/CXL subsystems Analyze failures and ensure coverage closure Contribute to verification methodology improvements and automation
Required Skills & Qualifications Strong experience in Design Verification using System Verilog and UVM Hands-on expertise in PCIe Gen 5 / Gen 6 (LTSSM, Equalization, Flow Control, AER, SR-IOV, etc.) Good understanding of CXL (CXL.io, CXL.cache, CXL.mem) protocols Experience with verification IPs (VIPs) for PCIe/CXL Proficiency in assertion-based verification (SVA) Strong debugging skills at block and SoC level Solid understanding of digital design fundamentals Experience with simulation tools (VCS, Questa, Xcelium, etc.)
Company Overview — Silicon Patterns Silicon Patterns is a specialized semiconductor engineering services company delivering comprehensive solutions across the entire silicon design and development lifecycle. The company excels in pre-silicon and post-silicon engineering services, helping clients accelerate product development while ensuring high quality and first-pass silicon success. With its headquarters in Hyderabad and offices in Bangalore and Raipur, Silicon Patterns also supports global teams in Malaysia and beyond, serving customers across Wireless, IoT, Automotive, and advanced computing domains.
Silicon Patterns offers end-to-end semiconductor solutions including
- RTL Design & IP Development
- Design Verification (DV) using modern methodologies like UVM/SystemVerilog
- Emulation, Pre- & Post-Silicon Validation
- Physical Design (PD) & DFT
- SystemC Modeling, Prototyping, and Silicon Bring-Up Support
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