Role & seniority: Senior Design Verification Engineer (5+ years in functional verification of complex SoCs/IPs)

Stack/tools: SystemVerilog, UVM, PCIe verification (Gen1–Gen4), LTSSM/TLP/DLLP/config space, RTL debugging, industry simulators (VCS/Questa/Xcelium), assertions (SVA)

Top 3 responsibilities

Develop and execute verification plans for PCIe-based IP/SoC designs
Build/enhance UVM/SystemVerilog verification environments; develop test cases, checkers, scoreboards, and assertions
Perform functional/regression/coverage-driven verification; debug RTL issues and verify PCIe protocol compliance

Must-have skills

5+ years in Design Verification
Expertise in SystemVerilog and UVM
Hands-on PCIe protocol verification (LTSSM, TLP/DLLP, config space, error handling)
Proficiency with simulators (VCS/Questa/Xcelium); strong debugging
Strong knowledge of SoC architecture and digital design fundamentals; SVA assertions

Nice-to-haves

PCIe VIP integration experience
Knowledge of AXI/USB/Ethernet; regression automation and scripting (Python/Shell/Perl)
Experience leading small verification modules
Location & work type: Not specified (location and employment type not provided)

Full Description

Company Description Chiplogic Technologies, founded in 2018, is a leading IP and Product Engineering Services company with expertise in Semiconductor, Systems, IoT, and AI/ML. The company excels in providing comprehensive solutions, including ODC and turnkey semiconductor design, system solutions from concept to silicon, and IoT and AI/ML services. Chiplogic also leverages its proprietary VISARD™ framework for video synthesis and real-time dynamics to deliver innovative solutions. Committed to excellence, Chiplogic drives groundbreaking advancements in the technology sector.

Role Description We are seeking an experienced Senior Design Verification Engineer with strong expertise in PCIe protocol verification. The ideal candidate must have a minimum of 5 years of hands-on experience in functional verification of complex SoCs/IPs, with deep knowledge of PCIe architecture and verification methodologies.

Key Responsibilities

Develop and execute verification plans for PCIe-based IP/SoC designs.
Build and enhance UVM/SystemVerilog-based verification environments.
Perform functional, regression, and coverage-driven verification.
Develop test cases, checkers, assertions, and scoreboards.
Debug RTL issues and work closely with design teams to resolve bugs.
Perform protocol compliance verification for PCIe (Gen1/Gen2/Gen3/Gen4 preferred).
Analyze coverage metrics and ensure closure (functional & code coverage).
Participate in design reviews and contribute to verification strategy definition.

Required Skills

Minimum 5+ years of experience in Design Verification (mandatory).
Strong expertise in SystemVerilog and UVM.
Hands-on experience in PCIe protocol verification (LTSSM, TLP/DLLP, configuration space, error handling, etc.).
Experience with industry-standard simulators (VCS/Questa/Xcelium).
Good understanding of SoC architecture and digital design fundamentals.
Experience in writing assertions (SVA).
Strong debugging and problem-solving skills.

Preferred Qualifications

Experience with PCIe VIP integration.
Knowledge of other high-speed protocols (AXI, USB, Ethernet) is a plus.
Experience in regression automation and scripting (Python/Shell/Perl).
Prior experience in leading small verification modules is an advantage.

Education

B. E./B.Tech/M.E./M.Tech in Electronics, Electrical, or related field.