Role & seniority: Senior Design Verification Engineer (6+ years) focused on UCIe IP/Subsystem verification.

Stack/tools: UCIe IP/subsystem verification; SystemVerilog; UVM or equivalent testbenches; RTL verification; scripting (Python, Perl, Tcl); digital design fundamentals; knowledge of PCIe/CXL a plus.

Top 3 responsibilities

Develop and execute verification plans for UCIe interfaces and chiplet IPs/subsystems.
Create/maintain testbenches (SystemVerilog/UVM) for subsystem and system-level verification; perform functional verification of RTL (simulation, debugging, coverage).
Integrate UCIe IP into Subsystem/SoC environments and verify correct operation in representative use cases; collaborate in reviews; mentor junior engineers.

Must-have skills

6+ years in design verification, specifically UCIe IP/subsystem verification
Proficiency with SystemVerilog, UVM, and industry-standard verification tools
Strong understanding of digital design, simulation, and chiplet-based architectures
Scripting skills (Python/Perl/Tcl) for automation and tool integration
Excellent problem-solving, communication, and teamwork abilities

Nice-to-haves

Knowledge of PCIe/CXL protocols
Experience verifying complex IP blocks and subsystems end-to-end
Experience mentoring or leading junior verification engineers

Location & work type: Not specified in posting.

Full Description

Position Overview We are seeking a highly skilled and experienced Design Verification Engineer with over 6 years of experience, specifically in UCIe IP and Subsystem verification, to join our innovative team. The ideal candidate will have a strong background in verification methodologies, System Verilog programming skills, excellent problem-solving skills, and the ability to work collaboratively in a fast-paced environment.

Key Responsibilities

Develop and execute verification plans for UCIe interfaces and chiplet interconnect IPs/subsystems.
Create and maintain testbenches (System Verilog/UVM or equivalent) for Subsystem and System-level verification testbenches.
Perform functional verification of RTL designs, including simulation, debugging, and coverage analysis.
Collaborate with design engineers to understand design specifications and requirements for IP and Subsystems.
Identify and resolve design and verification issues, ensuring high-quality and robust designs.
Integrate UCIe IP into Subsystem/SoC-level environments and verify correct operation in representative use cases.
Participate in design and verification reviews, providing technical expertise and insights.
Mentor junior verification engineers and provide technical guidance.

Qualifications

Bachelor’s or Master’s in electrical/Electronic Engineering, Computer Engineering, or a related field.
6+ years of experience in design verification, with a focus on UCIe IP/Subsystem verification (Knowledge of PCIe/CXL protocol is a plus).
Proficiency in verification languages and methodologies, such as System Verilog, UVM, and other industry-standard tools.
Strong understanding of digital design concepts, simulation, and chiplet-based systems/architectures.
Experience with scripting languages (e.g., Python, Perl, Tcl) for automation and tool integration.
Excellent problem-solving skills, strong communication and teamwork skills, with the ability to work effectively in a collaborative environment.
Proven track record of successfully verifying complex IP blocks and subsystems.
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Design Verification Engineer- UCIE