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Intel Corporation • India
Role & seniority: Senior Design Verification Engineer (technical lead) on Intel Silicon Chassis team
Stack / tools: SystemVerilog/UVM; ABV; co-simulation; HDL/verification languages; EDA tools; testbenches, VIPs, checks, complex behavioral models; NLP/ML-based flows; C/C++, Python; familiarity with AMBA (CHI/ACE/AXI), PCIe, UCIe, CXL
Define and implement verification strategy and methodology from IP to subsystems to SoC-level; drive first-pass silicon success
Build advanced verification environments, testplans, testbenches, checkers, VIPs; own functional signoffs and performance/power targets
Collaborate with architecture, design, and software; own multiple critical blocks; mentor verification engineers; establish technical standards
BS/MS in Electrical Engineering, CS, or related; 10+ years in design verification (IP DV, subsystem/SoC)
Deep expertise in interconnects, caches, memory subsystems; multiple bus protocols (AMBA, PCIe, UCIe, CXL); cache coherency models
Simulation-based verification (UVM/ABV), co-simulation; low-power verification; HDL/verification languages; EDA tools
Hands-on coding in SystemVerilog/UVM; C/C++; Python; reusable verification collateral
Strong communication and organizational skills; track record of on-time silicon delivery
Formal verification experience; emulation or FPGA-based verification
Experience with MMUs (SMMU/IOMMU) and interrupt con
Job Details: Job Description: Intel is seeking a highly technical Senior Design Verification Engineer for the Silicon Chassis team. In this senior technical leadership role, you will design and deliver next-generation chassis IPs, designed to scale across multiple product families. You will establish verification strategy and methodology, drive technical development with deep expertise, and deliver first-pass silicon success through best-in-class IP design and verification practices. This role requires exceptional technical depth across advanced DV methodologies and tools, combined with strong expertise in interconnect protocols, cache coherency, memory architecture, and software integration. You will be a key technical authority, owning multiple high-impact IP blocks and setting standards for technical excellence. Responsibilities: Design, develop, and deliver a comprehensive verification strategy and methodology that scales seamlessly from IP through subsystems to SoC-level verification Design and implement advanced verification environments, tools, and testplans enabling first-pass silicon success; develop sophisticated testbenches, checkers, VIPs, and complex behavioral models Collaborate closely with architecture, design, and software teams from initial product definition and specification reviews through implementation, bringup, and productization phases; balance complexity and ensure timely, high-quality execution Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams Champion innovation across simulation, formal, and accelerated verification methodologies; develop and evaluate new ML-based flows and hybrid software frameworks Mentor and develop verification engineers; establish verification best practices and drive organizational technical excellence Qualifications: Minimum Qualifications: BS/MS in Electrical Engineering, Computer Science, or related field, with 10+ years of relevant experience in design verification; extensive background in IP DV with significant, demonstrated experience in subsystem and SoC-level verification. Proven deep expertise in interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; cache coherency and memory consistency models. Demonstrated experience in verification of global functions including debug, trace, clock & power management, RAS, QoS, and security features. Strong background in simulation-based verification methodologies including UVM, ABV, and co-simulation; proficiency in low-power verification techniques, HDL/verification languages, and industry-standard EDA tools. Advanced hands-on coding proficiency across SystemVerilog/UVM, software programming languages (C/C++), scripting (Python), and build systems; established track record of developing and delivering highly configurable and reusable verification collateral. Excellent communication and organizational skills with a proven track record of delivering on-time, high-quality silicon and establishing technical standards. Preferred Qualifications: Demonstrated experience with formal verification apps and emulation or FPGA based verification. Prior work with system IPs such as MMUs (SMMU or IOMMU) and interrupt controllers, and working knowledge of the associate software stacks. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology. Benefits Internships Life at Intel Locations Recruitment Process Discover your place in our world-changing work.