Role & seniority: Verification Engineer in the AECG Group (mid-to-senior level; front-end design/integration focus)

Stack/tools: IP-level ASIC verification; Verilog, SystemVerilog; UVM-based testbenches and verification components (monitors, scoreboard, checkers); scripting (Python/Perl); familiarity with HLS tools/process; PCIe, CXL, NVMe, Ethernet protocols

Top 3 responsibilities

Collaborate with architects, hardware, firmware, and software teams to understand features to verify; develop test plans considering hardware/software interactions
Code IP/SoC-level UVM testbenches, verification components, directed and random tests; build coverage and assertions
Run regressions, debug failures, and drive high-quality design functionality, performance, and implementation

Must-have skills

Proficiency in IP-level ASIC verification; Verilog/SystemVerilog; UVM-based verification frameworks
Strong scripting in Python/Perl; ability to automate verification flows
Good Computer Architecture/systems knowledge; effective cross-site communication

Nice-to-haves

Leadership or mentorship experience; experience across ASIC project lifecycle (planning to tape-out)
Familiarity with PCIe, CXL, NVMe, or Ethernet protocols
Exposure to simulation acceleration, efficiency tools, and HLS processes

Location & work type: San Jose, CA; Hybrid work arrangement; role not eligible for visa sponsorship

Full Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE

As a verification engineer in the AECG Group, you will help bring to life cutting-edge FPGA, ASICs for variety of target customers. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success.

THE PERSON

You have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBLITIES

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers
Build the directed and random verification tests
Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality

PREFERRED EXPERIENCE

Proficient in IP level ASIC verification
Expert in Verilog, System Verilog, Object Oriented programming
Expert in developing UVM based verification frameworks and testbenches
Scripting and automation of verification processes and flows
Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
Good Computer Architecture, systems knowledge
Comfortable in python / perl and editing / maintaining scripts
Exposure to leadership or mentorship is an asset
Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out

IP Verification Engineer