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Chiparama • San Francisco, California, United States
About the Role We are seeking an experienced Verification Engineer to develop test plans, build verification environments, and ensure functional correctness of complex hardware IPs and SoCs. The ideal candidate will have deep expertise in SystemVerilog/UVM-based verification meth
About the Role We are seeking an experienced Verification Engineer to develop test plans, build verification environments, and ensure functional correctness of complex hardware IPs and SoCs. The ideal candidate will have deep expertise in SystemVerilog/UVM-based verification methodologies, as well as experience with simulation, formal verification, and emulation platforms.
Key Responsibilities Develop and execute test plans for block-level, IP-level, and SoC-level verification. Build and maintain UVM/SystemVerilog testbenches (drivers, monitors, agents, checkers, scoreboards). Write test cases and directed/random sequences to achieve coverage goals. Debug failures in collaboration with design, architecture, and software teams. Track and drive functional + code coverage closure. Leverage formal verification, emulation, and FPGA prototyping to validate cutting-edge designs. Document verification methodology, results, and best practices.
Qualifications Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or related field. 5–20+ years of hands-on verification experience at block/IP/SoC level. Strong knowledge of SystemVerilog, UVM methodology, and RTL design fundamentals. Proficiency in debugging with simulation tools (VCS, Questa, Xcelium, etc.). Experience with ARM AMBA protocols (AXI, AHB, APB) and memory/cache subsystems. Hands-on knowledge of coverage-driven verification and writing assertions (SVA).
Preferred Skills Experience with ARM CHI protocol or other coherency protocols. Familiarity with formal verification tools (JasperGold, OneSpin). Knowledge of emulation/prototyping platforms (Cadence Palladium, Mentor Veloce, Synopsys Zebu, FPGA prototyping). Scripting skills in Python/Perl/TCL for automation and regression management. Exposure to RAS (Reliability, Availability, Serviceability) features and QoS in interconnect fabrics.