Design Verification Manager (ASIC / RTL) — 12+ Years
Best NanoTech • Bengaluru, Karnataka, India
Role & seniority: Senior technical leadership; hands-on ASIC/RTL Design Verification leadership, overseeing a 10+ member DV team.
Stack/tools: SystemVerilog (testbench, assertions, coverage), UVM/OVM, simulation/debug across Synopsys/Cadence/Mentor (Siemens EDA), scripting (Python/Perl/Shell/Tcl), HDL/HVL (Verilog/VHDL/SystemC as needed); AMBA (AXI/AHB), JTAG; regression/verification infrastructure and signoff tooling.
Top 3 responsibilities
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Lead and manage Design Verification team (planning, execution, reviews, delivery commitments)
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Define/implement verification strategy and scalable testbench architecture; own UVM/OVM adoption and best practices
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Oversee simulation environments, automation, debug, regression, coverage-driven signoff, and silicon bring-up support
Must-have skills
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12+ years hands-on ASIC/RTL DV experience with full DV lifecycle ownership
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Proven leadership for large DV teams (10+ members)
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SystemVerilog, UVM/OVM, EDA toolchains (Synopsys/Cadence/Mmentor Siemens), scripting (Python/Perl/Shell/Tcl)
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HDL/HVL exposure (Verilog/VHDL/SystemC), AMBA protocols, JTAG
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Experience with regression, signoff readiness, and processor/subsystems verification
Nice-to-haves
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Verification of processor subsystems (ARM/RISC) and integration challenges
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Debug turnaround optimization, fast root-cause analysis, and post-silicon bench/application support
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Automation for metrics, dashboards, and triage
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Location & work type: Ben
Full Description
Location: Bengaluru, India
Experience: 12+ years
Employment Type: Full-time
Role Summary
Senior technical leadership role responsible for driving ASIC/RTL design verification execution and strategy across complex SoC/subsystem programs. You will lead a 10+ member verification team, own verification methodology and delivery quality, and collaborate with design, validation, and silicon teams through bring-up.
Key Responsibilities
Lead and manage a Design Verification team of 10+ engineers; drive planning, execution, reviews, and delivery commitments. Define and implement verification strategy and scalable SystemVerilog testbench architecture. Own and oversee OVM/UVM methodology adoption, guidelines, and best practices across projects. Manage simulation environments and regression infrastructure across Synopsys / Cadence / Mentor (Siemens EDA) toolchains. Drive automation and scripting for productivity (regression, log parsing, metrics, triage, dashboards). Lead debug and root-cause analysis for complex functional issues; improve debug turnaround time and closure discipline. Oversee verification of processor subsystems (e.g., ARM/RISC-based blocks), including integration-level verification readiness. Manage creation and automation of validation suites, including coverage-driven signoff expectations and reporting. Guide silicon bring-up support and post-silicon debug readiness (bench/application support as applicable).
Ensure quality, completeness, and consistency of verification deliverables: plans, testbenches, coverage, signoff reports, and release documentation.
Required Qualifications
B. E / B.Tech / M.E / M.Tech in Electrical / Electronics / related discipline
- 12+ years of hands-on ASIC/RTL Design Verification experience with strong ownership of full DV lifecycle
- Demonstrated leadership experience managing and mentoring large DV teams (10+ members)
Technical Requirements (What You’ll Work With)
SystemVerilog (testbench architecture, assertions, coverage) UVM / OVM methodology and reusable verification components
Simulation / debug across EDA platforms: Synopsys / Cadence / Mentor (Siemens EDA)
Scripting & automation: Python / Perl / Shell / Tcl/Tk
HDL/HVL exposure: Verilog / VHDL / SystemC (as needed)
Protocols/interconnects: AMBA (AXI/AHB), JTAG Gate-level simulation and debug concepts; regression and signoff readiness Processor subsystems verification and integration challenges Silicon testing / bring-up support mindset (bench/application enablement)
