ASIC/SoC Design Verification Engineer
TetraMem - Accelerate The World • San Jose, California, United States
Salary: $110,000 - $300,000 / year
Role & seniority: Senior/Staff SoC Verification Engineer (8+ years experience; PhD with 3+ years acceptable)
Stack/tools: UVM/OVM, Semiformal, assertion-based verification; hardware/software co-verification; Verilog, SystemVerilog; Python/Perl/TCL/Shell; C/C++; SystemC; RTL and post-P&R gate-level verification; testbench development; constrained-random and directed test cases; verification infrastructure and regression tooling; familiarity with MIPI, AMBA (APB/AHB/AXI); RISC-V/ARM/DSP cores
Top 3 responsibilities
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Define, document and implement detailed test plans for SoC design verification; build/maintain automation verification infrastructure
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Develop reusable testbenches, constrained-random/directed tests, and verification-related behavioral modules for block and system levels; drive coverage and regression strategies
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Debug root causes of simulation failures; support post-silicon validation; mentor junior engineers and drive verification efficiency
Must-have skills
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8+ years of relevant experience (or PhD with 3+ years)
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Deep expertise in UVM/OVM, Semiformal, assertion-based verification; hardware/software co-verification
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Proven track record in verification infrastructure, test planning, coverage closure, testbench/testcase development for function/performance
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Proficiency in Verilog/SystemVerilog, Python/Perl/TCL/Shell, C/C++, SystemC; experience with RTL and post-P&R gate-level verification
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Familiarity with MIPI, AMBA bus protocols,
Full Description
Responsibilities
Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance Develop reusable testbench, constrained-random/directed test cases, and verification associated behavioral module for both of block levels and system levels Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out Work with design engineers to debug and identify root causes of simulation failure Support test engineers for post-silicon validation Mentor and coach team members and junior engineers. Drive verification efficiency
Requirements
MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodology Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and testcases development for function/performance verification Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core Experience in verifying designs at both of RTL level and post-P&R gate level Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team
Experience in one or more of the following areas considered a strong plus
Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators Experience in verifying mix-signal design and interface of digital and analog Experience of design verification for highspeed IO such as PCIE and DDR
Salary Range: $110,000 - $300,000 / year
