ASIC/SoC Design Verification Engineer SG
TetraMem - Accelerate The World • Singapore, Singapore
Salary: SGD 80,000 - SGD 180,000 / year
Role & seniority: Senior Verification Engineer / Lead verification role with mentoring responsibilities; capable of technical leadership in a startup environment.
Stack/tools: SoC verification; UVM/OVM; Semiformal and assertion-based verification; hardware/software co-verification; Verilog, SystemVerilog; Python/Perl/TCL/Shell scripting; C/C++; SystemC; experience with MIPI, AMBA (APB/AHB/AXI); RISCV/ARM/DSP cores; RTL and post-P&R gate-level verification.
Top 3 responsibilities
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Define, document, and implement test plans for SoC design verification; build/maintain automation verification infrastructure.
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Develop reusable testbenches, constrained-random/directed testcases, and verification modules for block and system levels; define/measure functional coverage and close verification holes.
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Debug/fix simulation failures with design engineers; develop regression strategy/tools; support post-silicon validation; mentor team members.
Must-have skills
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MS (8+ years) or PhD (3+ years) in EE/CE/CS or related field.
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Deep expertise in UVM/OVM, Semiformal, assertion-based verification; hardware/software co-verification.
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Proven experience building verification infrastructure, test planning, coverage closure, testbenches, and test cases for function/performance verification.
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Proficiency in Verilog/SystemVerilog, scripting languages (Python/Perl/TCL/Shell), C/C++, SystemC; familiarity with MIPI, AMBA, RISCV/ARM/DSP.
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Experience with RTL and post-P&R ga
Full Description
Responsibilities
Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance Develop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levels Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out Work with design engineers to debug and identify root causes of simulation failure Support test engineers for post-silicon validation Mentor and coach team members and junior engineers. Drive verification efficiency
Requirements
MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodology Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and testcases development for function/performance verification Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core Experience in verifying designs at both of RTL level and post-P&R gate level Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team
Experience in one or more of the following areas considered a strong plus
Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators Experience in verifying mix-signal design and interface of digital and analog Experience of design verification for highspeed IO such as PCIE and DDR
Salary Range: S$80,000 - S$180,000 / year
