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ADN Group • Austin, Texas, United States
Role & seniority: Mixed-Signal Verification Engineer, Senior (5+ years total experience; MSV-focused)
Stack/tools: UVM-based verification; SystemVerilog / Verilog; analog/digital mixed-signal modeling; Cadence Virtuoso (schematics/sim); waveform tools; cross-tool flow with Synopsys; Verdi (preferred)
Develop and execute verification strategies for mixed-signal designs using UVM; create/maintain analog behavioral models with design teams
Write, run, and debug SystemVerilog/UVM testbenches for mixed-signal blocks; validate models across abstraction levels
Perform unit/subsystem/top-level simulations, analyze results, troubleshoot issues, and contribute to test plans and verification flows
5+ years total experience; strong behavioral modeling for analog design in digital verification
Proficiency in Verilog/SystemVerilog; UVM methodologies and tools (simulators, waveform viewers, automation, coverage)
Experience with mixed-signal designs and digital verification tools; ability to debug complex verification environments
Familiar with Cadence Virtuoso (schematics/simulation) and cross-tool familiarity (Cadence/Synopsys)
Experience with high-speed/high-performance communication designs
Reusable/scalable verification environments and testbenches
Waveform debugging tools (e.g., Verdi); strong cross-functional collaboration
Location & work type: Austin, TX; on-site, full-time, f
Job Title: Mixed Signal Verification Engineer
Location: Austin, TX
Domain: Information technology (IT)
Duration: Fulltime Role
Experience: 5-10 Years
Visa: Any Visa
NOTE: NO C2C
Mixed Signal Verification Engineer Client Our client is a Series-D semiconductor innovator, specializing in programmable coherent DSP (digital signal processing) solutions for cloud and AI infrastructure, a foundational technology that enables faster and more efficient transmission within and between AI data centers. The firm is empowering the future of AI infrastructure and cloud connectivity with DSP innovations. The firm recently came out of stealth with $180MM funding and is backed by storied venture investors including Kleiner Perkins, Spark Capital, Mayfield and Fidelity Investments.
About The Position We are seeking a Mixed-Signal Verification Engineerto support the verification of high-speed communication designs that integrate complex digital and analog components. This role focuses on building and validating verification environments that bridge digital verification methodologies with analog design behavior. This is a hands-on role working closely with analog designers, digital designers, and verification engineers to ensure correctness and performance across unit-, subsystem-, and full-chip simulations. Location: Austin, TX Work Model: On-site, five days per week (required)
Develop and execute verification strategies for mixed-signal designs using UVM-based methodologies
Create and maintain behavioral models for analog blocks in collaboration with analog design teams
Write, run, and debug SystemVerilog / UVM testbenches for mixed-signal blocks
Validate behavioral models through simulation and debug across multiple abstraction levels
Perform and troubleshoot unit-level, subsystem-level, and top-level mixed-signal simulations
Analyze simulation results, identify root causes, and collaborate with design teams to resolve issues
Contribute to test plans, verification documentation, and continuous improvement of verification flows
Minimum Qualifications.
2+ years of experience in mixed-signal verification, behavioral modeling, or closely related verification roles
Strong experience with UVM-based verification methodologies
Proficiency in Verilog / SystemVerilog
Experience working with mixed-signal designs using digital verification tools
Working knowledge of analog design concepts sufficient to model and verify analog behaviour
Ability to debug complex verification environments and communicate findings clearly
5+ years of total experience Experience in Behavioural Modelling (BM) of Analog design for digital verification
Experience in Verilog/System Verilog coding Experience in Virtuoso Schematics tools
Experience in UVM Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection.
Proven experience in developing scalable and portable test cases.
Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment.
Preferred Qualifications
Experience using Cadence Virtuoso schematic and simulation environments
Familiarity with both Cadence and Synopsys toolchains
Experience developing scalable and reusable verification environments and testbenches
Exposure to high-speed or high-performance communication designs
Experience with waveform debug tools (e.g., Verdi)
Strong collaboration skills in cross-functional engineering team
Arushi Khanna | Associate - Hiring & Recruitment
Email: arushi@nsitsolutions.com
&
Vishal (Victor) Verma | Assistant Manager
NS IT Solutions