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UST • George Town, Penang, Malaysia
Role & seniority: Systems Validation Engineer, mid-level (3+ years in validation/debug)
Stack/tools: PC/board tech (x86, APU/CPU/GPU, power management), Windows & Linux, system-level validation (Unit/Integrity/System levels), scripting: Python, C, Perl, Ruby; automation/validation farm familiarity
Define post-silicon test strategy and end-to-end validation plans; lead issue debugging and fast-response resolution
Collaborate with Architecture, Design, and cross-functional hardware/software teams; drive work from planning to execution
Improve system-level test methodologies, produce management reports, and propose risk-based solutions
3+ years in validation/debug in related industry
Strong PC hardware background; familiarity with x86, APU/CPU/GPU, system features, and power management
Experience across unit/integrity/system-level validation; excellent cross-geography communication
Proficiency with Windows/Linux; scripting capability (Python or equivalent)
Automation farm experience; hands-on automation feature development
Experience with multi-functional hardware/software collaboration and complex issue debugging
Knowledge of validation across pre/post-silicon stages and related methodologies
Location & work type: Location not specified; work type not specified in provided information