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UST • Penang, Malaysia
Role & seniority: Systems Validation Engineer, mid-level (3+ years in validation/debug)
Stack/tools: PC hardware/architecture focus (x86, APU/CPU/GPU), Windows and Linux, scripting in Python/C/Perl/Ruby; automation/validation farm experience a plus
Define test strategy and post-silicon validation plans; lead end-to-end validation from planning to issue debug
Collaborate with architecture, design, pre-silicon, hardware, and software teams; debug complex issues; deliver risk-focused management reports
Improve system-level integration/test methodologies; develop and enhance automation features per requirements
Strong PC technology background; familiarity with x86 ecosystems, system features, and power management
Proven experience in system-level validation (unit/integrity/system levels) and cross-functional collaboration
Proficiency with Windows and Linux; able to communicate across geographies
Automation farm experience; scripting/coding capability (Python, C, Perl, Ruby)
Experience driving validation plans in global teams and technical debugging of silicon/platform issues
Location & work type: Location not specified; full-time position