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Comprehensive Resources Inc • Mountain View, California, United States
Role & seniority: HSIO Validation Engineer; senior-level (10+ years total, with ~3+ years in HSIO validation focusing on MIPI M-PHY/USB3.2)
Stack/tools: MIPI M-PHY, USB 3.2, Linux, Python, Shell; BERTs, JTAG, Oscilloscope, T32, VNA; PCB schematics/layout; PyVISA, Pytest, Pandas, Pywinauto, PyAutoGUI; ATE/SLT screens; manufacturing/test automation
Own bench-level design validation and electrical compliance for high-speed serial interfaces (MIPI M-PHY, USB 3.2) and ensure certification readiness across PVT
Characterize signal/power integrity with oscilloscopes, BERTs, VNA; perform advanced analyses (eye diagrams, jitter decomposition, RX tolerance)
Collaborate with cross-functional teams to root-cause PHY-level issues and protocol link-up failures; drive design corrective actions; develop Python-based lab automation; contribute to end-to-end test solutions
10+ years experience; 3+ years in high-speed I/O validation (MIPI M-PHY or USB3.2)
Linux, Python, Shell scripting
Lab equipment: high-bandwidth oscilloscopes, BERTs, JTAG, T32, VNA
IP bring-up, validation, PCB schematics/Layout, manufacturing support; hardware debugging from schematics/layout
MPHY/USB-IF compliance testing and official certification; advanced equalization techniques
Python automation for measurements and data handling; PyVISA, Pytest, Pandas, Pywinauto, PyAutoGUI; signal integrity principles
Position: HSIO Validation Engineer
Location: Mountainview ,CA
Exp: 10+ years
Rate: case to case basis HSIO Validation Engineer
Key skills: HSIP, MIPI M-PHY, USB 3.2, Linux, Python, Shell, BERTs, JTAG, Oscilloscope, T32, VNA, PCB schematics, PyVISA, Pytest, Pandas, Pywinauto, PyAutoGUI Own bench level design validation and electrical compliance for High-speed serial interfaces (MIPI M-PHY, USB3.2), ensuring certification rediness across PVT operating conditions. Characterize signal and power integrity using oscilloscopes, BERTs and VNA to perform advanced analysis including eye diagrams, Jitter decomposition, and receiver (RX) tolerance Collaborate with cross functional teams to root-cause complex PHY-level electrical issues and protocol link-up failures, driving design corrective actions Design python-based automation to improve lab efficiency and partner with architecture teams to implement end-to-end manufacturing test solutions. Influence next generation product design via developing ATE/SLT screens to reduce defective part per million(DPMT) 10+ Years of experience 3 years of experience in high-speed I/O validation, Specifically focussing on MIPI M-PHY or USB3.2 electrical compliance & characterization Experience in Linux, Python & Shell scripting Experience with lab equipment including high-bandwidth oscilloscopes, BERTs, JTAG, T32 and Vector Network analysers(VNA) Experience in IP bringup, validation, PCB schematics/Layout and manufacturing support Experience debugging hardware issues using schematics and layouts Experience with MPHY and USB-IF compliance testing and the official certification process Experience with advanced equalization techniques and their characterization Experience with python based automation(electrical measurement equipment, environmental chambers, etc) and scripting (data analysis, manipulation, visualizations)
Experience with one or more of the following: PyVISA, Pytest, Pandas, Pywinauto, PyAutoGUI Experience with signal integrity principles and measurement techniques.