Full Description

We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world.

Internship Experience

At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide—and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today!

Mission Statement

Our mission is to fuel today’s innovations and spark tomorrow’s creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive—both at work and beyond.

What You’ll Be Doing

Define and develop complex digital and analog verification environments using SystemVerilog, UVM, and formal verification methodologies. Create verification test plans, environment documentation, and user documentation for testbench components. Develop functional specifications for digital and analog verification sub blocks and overall testbench architecture. Run RTL and mixed signal (digital/analog) simulations, analyze results, and collaborate with design teams to optimize the design. Develop behavioral models using Verilog/SystemVerilog. Identify design issues across digital and analog domains, propose corrective actions, and support debug workflows. Improve verification automation, toolchains, and internal workflows.

What You’ll Need

Currently pursuing a degree in Electronics, Computer Engineering, Automation, or a related field. Good understanding of digital electronics with basic analog knowledge. Working knowledge of Verilog, VHDL, and SystemVerilog for modeling, simulation, and verification.

Proficiency in at least one programming language: Python, Perl, C, C++, or MATLAB. Understanding of UVM or similar verification methodologies is an advantage. Ability to prepare and maintain clear technical documentation. Experience using digital, analog, or mixed-signal simulation tools within a Linux-based environment. Strong communication skills and ability to build relationships within a collaborative team environment. Communicative level of English (spoken and written). Fast learner, open to new tools, methods, and technologies. Analytical thinking and effective problem-solving skills. Reliable, organized, and able to work independently when needed.

Key Program Facts

Program Length: 6 months.

Location: Gdansk office, Poland.

Working Model: Onsite Full-Time preferable

Start Date: May 2026

Equal Opportunity Statement

Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us.