Full Description

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

DESCRIPTION

APPLE INC has the following available in Orlando, Florida. Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (Specman/System Verilog), and logic simulators to verify complex graphics processing unit (GPU) register-transfer level (RTL) designs. Develop and drive verification plans that include strategies for tests, checks, and coverage models. Estimate time needed to complete verification plan items to support project scheduling. Generate constrained random and directed tests to implement verification plans. Run simulations and debug issues where hardware and software results differ. Create reusable testbench components to monitor and check functionality of various RTL designs. Creating functional coverage points, analyze coverage, and enhance test environment to target coverage holes. Create automated verification flows for graphics core verification. Review hardware design specifications and collaborate with architects to identify functional and performance bugs. 40 hours/week.

MINIMUM QUALIFICATIONS

Bachelor’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field and 1 year of experience in the job offered or related occupation. 1 year of experience with each of the following skills is

required: Utilizing System Verilog coding skills to develop reusable testbench environments that consist of constraint random and directed test stimulus, monitors and checks for transactions, and functional coverage points. Utilizing Object Oriented Programming principles, including encapsulation, abstraction, inheritance and polymorphism, to create cycle/transaction accurate behavior models to validate various RTL design functionality. Utilizing UVM skills and standard verification methodology to develop modular, scalable, and reusable testbench environments that support verification plan objectives. Developing a comprehensive design verification and coverage model plan to facilitate accurate estimation of effort for project schedules and timelines. Utilizing Scripting language (Python, Ruby or Perl) to facilitate automation of creating regression result charts and other verification flows/components for re-use. Utilizing experience with industry standard Simulators (Cadence or VCS) to compile, run, and profile testbench environments used to validate RTL design blocks. Using waveform debuggers, such as Verdi, Indago, or similar tools, to analyze signal traces captured from simulations or actual hardware. Experience with basic UNIX command-line utilities for manipulating and editing files, searching for data, and scripting or automating common sequences of operations. Experience in complex algorithms, including designing, implementing, and debugging hardware functional or performance reference models.