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Apple • Munich, Bavaria, Germany
Role & seniority: Design Verification Engineer (mid- to senior-level implied)
Stack/tools: SystemVerilog, UVM/OVM, mixed-signal verification basics, hardware description languages, logic simulators, test benches, constrained random testing, coverage tooling, assertion-based and formal verification
Establish verification methodology and test plans in collaboration with design leads
Build/maintain verification environments and test benches; develop automated verification flows; write directed/constrained-random tests
Run simulations, debug design/environment issues, develop coverage points, analyze/close coverage holes; sign-off for RTL freeze and tape-out
Knowledge of object-oriented programming
Basic mixed-signal verification concepts
MS/BS in Computer Science, Electrical Engineering, or equivalent
English fluency
Experience scalable portable test-benches and constrained-random environments
Coverage modeling, coverage analysis, and coverage-driven verification
Assertion-Based Verification and Formal Verification
Advanced SystemVerilog/UVM experience; good communication and collaboration
Location & work type: Not specified in the description; no explicit location or work-type details provided
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a results-oriented and highly committed Design Verification Engineer. As a member of our multifaceted group, you will have the unique opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every day. We are looking for a Design Verification Engineer in our team, who will enable bug-free first silicon for our mixed-signal designs, in close collaboration with Digital and Analog Design engineers. The responsibilities involve all phases of pre-silicon verification including establishing design verification methodology and test-plan development. Additional responsibilities will involve verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
DESCRIPTION
In this role you will develop verification plans in coordination with design
leads and architects. Your responsibilities will include: - Building and maintaining verification test bench components and environments - Generate directed and constrained random tests - Run simulations and debug design and environment issues - Build functional coverage points, analyze coverage, and improve test environment to target coverage holes - Craft automated verification flows for block and chip level verification - Apply knowledge of hardware description languages, hardware verification languages (SystemVerilog), methodology (UVM/OVM), and logic simulators to verify complex designs - Work with other block and chip level engineers to ensure a flawless verification flow
MINIMUM QUALIFICATIONS
Knowledge of Object Oriented Programming Basic knowledge of mixed signal verification MS/BS in Computer Science, Electrical Engineering or equivalent Fluency in English language is required
PREFERRED QUALIFICATIONS
Excellent communication and interpersonal skills combined with the ability to collaborate Experience developing scalable and portable test-benches Experience with constrained random verification environments Experience defining coverage space, writing coverage model, analyzing results Experience with Assertion Based Verification Experience in Formal Verification Advanced knowledge of SystemVerilog and UVM