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Apple • Munich, Bavaria, Germany
Role & seniority: Design Verification Engineer (mid‑level to senior level implied)
Stack / tools: Python, Perl, or TCL; SystemVerilog; UVM; coverage-driven verification; constrained-random stimuli; assertion-based verification; formal verification; experience with mixed-signal design
Develop and maintain verification components and test benches for chip and block level verification (including automated checking and automated coverage collection)
Execute design verification: debugging, coverage analysis/enhancements, and results interpretation
Plan design verification and co-verify design and firmware in collaboration with design/concept engineering
MS/BS in Electrical/Computer Engineering or equivalent
Strong communication and collaboration skills; able to work in a team and take ownership
Proficiency in Python, Perl, or TCL; fluent English
Advanced verification knowledge/tools (UVM, SystemVerilog)
Object-oriented programming; coverage-driven verification with constrained random stimuli
Assertion-based verification; formal verification
Track record in digital/analog or mixed-signal design and debugging
Location & work type: location and employment type not specified in provided text
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a results-oriented and highly committed Design Verification Engineer. As a member of our multifaceted group, you will have the unique and exciting opportunity to craft upcomingproducts that will delight and encourage millions of Apple’s customers every day. We are looking for a Design Verification Engineer in our team, who will enable bug-free first silicon for our mixed-signal designs, in close collaboration with Digital and Analog Design engineers. The responsibilities include all phases of pre-silicon verification including establishing design verification methodologies and test-plan development.
DESCRIPTION
Your responsibilities will include: - To develop and maintain verification components and test benches for chip level and block level verification including automated checking, automated coverage collection, and constrained random stimuli - To execute design verification including design and test bench debugging as well as coverage analysis and enhancements - To plan design verification and to analyse results in collaboration with design and concept engineering - To co-verify design and firmware
MINIMUM QUALIFICATIONS
MS/BS in Electrical Engineering, computer engineering or equivalent Excellent communication and interpersonal skills, combined with the ability to collaborate Ability to work well on a team, take ownership and motivate self and others Experience with Python, Perl or TCL Fluent English skills
PREFERRED QUALIFICATIONS
Advanced knowledge of verification methods and tools like UVM and System Verilog Good knowledge of Object Oriented Programming Coverage driven verification leveraging constrained random stimuli Assertion based verification Experience in Formal Verification Track record in digital or analog design or design debugging, preferable with mixed-signal designs