
Senior ASIC Verification Engineer, Low Power Audio Subsystems/AI
Qualcomm • Markham, Ontario, Canada
Salary: $104,900 - $154,900 / year
Role & seniority: Lead ASIC verification engineer (replacement position) in Qualcomm Canada ULC, focusing on low power AI audio subsystems.
Stack/tools
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HVL: SystemVerilog testbench (UVM), SystemC
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HDL: Verilog, SystemVerilog
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Programming/scripting: C/C++, Python, Perl, tcsh, GNU Make
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Architectures: AHB/AXI interconnects, ARM v7/v8, MMU, security concepts
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Verification emphasis: test bench development, assertions, functional coverage, debug flows
Top 3 responsibilities
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Contribute to core verification during pre/post-silicon phases of next-gen ASICs; drive test plan development, execution, and verification closure with design/verification teams
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Create/maintain test benches, assertions, and coverage models with reuse and scalability; lead automation of development flows; identify and drive improvements
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Lead complex debug activities across the development cycle; provide technical supervision and exemplify lead-by-example; define verification methodology and tests with design
Must-have skills
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2+ years in ASIC design/verification or related work
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SystemVerilog/UVM experience; Verilog/SystemVerilog; basic C (or C++)
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Strong knowledge of digital circuits and event-driven simulators
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Experience or familiarity with audio domains, bus/interconnect (AHB/AXI), ARM v8/v7, caches, MMU, security
Nice-to-haves
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Additional audio domain knowledge (MP3, MIDI, etc.)
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Perl, Python, tcsh, GNU Make proficiency
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Automotive safety co
Full Description
Company
- Qualcomm Canada ULC
Job Area
- Engineering Group, Engineering Group > ASICS Engineering
General Summary
- What we are doing has not been done.
- Shape the future of low power AI subsystems.
- Push the boundaries on features and performance.
- Qualcomm Technologies Audio products are designed to offer premium wireless connectivity, high levels of integration, immersive sound quality, and on-device AI for smart audio and context aware applications. An ultra-low power subsystem within a low power SoC; a chip-within-a-chip HW block incorporating multiple always-on IP's, design execution within this group requires solving ground-breaking challenges and multiple power domain crossing issues.
- As we pioneer new and/or improved functionality, we innovate to minimize power consumption.
- Make a difference, join a team on the cutting edge and become an integral part of Qualcomm’s growth and momentum. Replacement Position.
As a lead member of the team
- Contribute to core verification during the pre/post silicon phase of next generation ASICs through simulation
- Drive test plan development, execution and verification closure in conjunction with the design and verification teams
- Contribute to creating/maintaining a test bench, assertions, and functional coverage models with scalability and reuse as key goals
- Contribute to implementing flows to automate development processes. Identify areas for improvement and drive them to completion
- Lead complex debug activities through the development cycle (pre and post-silicon)
- Provide technical supervision to other engineers and have the ability to lead by example
- Work closely with design to define verification methodology, Provide test plans and develop required tests.
Requirements
- 2+ years ASIC design, verification, or related work experience.
Hardware verification languages (HVL): SystemVerilog testbench (UVM), and/or SystemC, Hardware description languages (HDL): Verilog and SystemVerilog Good working experience with C (basic level or C++ sufficient)
Knowledge in one or more of the following disciplines is preferred: Audio (MP3, MIDI, etc.), Bus/interconnect (AHB, AXI), CPU (ARM v8/v7, Cache, MMU, security, etc.). Strong knowledge of digital circuits and event-driven simulators
Preferred Qualifications
Knowledge in one or more of the following disciplines is preferred: Audio (MP3, MIDI, etc.), Bus/interconnect (AHB, AXI), CPU (ARM v8/v7, Cache, MMU, security, etc.). Strong knowledge of digital circuits and event-driven simulators Knowledge of Perl, tcsh, Python and GNU Make is a strong asset Experience with automotive safety concepts and standards such as ISO26262
Minimum Qualifications
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, or related work experience.
- OR
- Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, or related work experience.
- OR
- PhD in Science, Engineering, or related field.
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Pay range and Other Compensation & Benefits
- $104,900.00 - $154,900.00
- The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer.
- If you would like more information about this role, please contact Qualcomm Careers.