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The Versatile Club • Bengaluru, Karnataka, India
Role & seniority: DFT Engineer, mid-senior (4+ years in ASIC/SoC environments)
EDA: Synopsys DFT Compiler, TestMAX, TetraMAX; Cadence Modus
Optional: Siemens Tessent / FastScan (preferred)
Techniques: Scan, ATPG, MBIST; memory test algorithms
Scripting: TCL, Perl, Python
Interfaces: RTL design flows, STA constraints, silicon bring-up
Implement and verify Scan, ATPG, and MBIST for complex SoCs
Pattern generation, coverage analysis, debugging; integrate/validate MBIST
Coordinate with RTL and Physical Design for DFT signoff; develop automation for DFT flows
4+ years DFT experience in ASIC/SoC
Hands-on with Synopsys (DFT Compiler, TestMAX, TetraMAX) and Cadence Modus
MBIST architecture knowledge and memory test techniques
Fault models (stuck-at, transition, path delay)
Scripting in TCL, Perl, or Python; familiarity with RTL, STA constraints, silicon bring-up
Siemens Tessent / FastScan experience
Deeper memory test/MBIST algorithm expertise; automation experience
Location & work type: not specified; provide details if known
We are seeking experienced DFT Engineers with strong expertise in Scan, ATPG, and MBIST for SoC/ASIC designs. The role focuses on implementation, pattern generation, and verification of DFT features to ensure high test coverage and silicon readiness.
Key Responsibilities
Implement and verify Scan, ATPG, and MBIST for complex SoCs.
Perform pattern generation, coverage analysis, and debug.
Integrate and validate MBIST with appropriate memory test algorithms.
Coordinate with RTL and Physical Design teams for smooth DFT integration and signoff.
Develop automation scripts to streamline DFT flows.
Required Skills
Minimum 4 years of DFT experience in ASIC/SoC environments.
Hands-on Expertise With EDA Tools Such As
Synopsys (DFT Compiler, TestMAX, TetraMAX)
Cadence Modus
Preferred: Experience with Siemens Tessent / FastScan.
Strong understanding of fault models (stuck-at, transition, path delay).
Knowledge of MBIST architecture and memory test techniques.
Scripting proficiency in TCL, Perl, or Python.
Familiarity with RTL design flows, STA constraints, and silicon bring-up
Skills: mbist,scan,silicon,dft,automatic test pattern generation (atpg),asic design,soc,soc/asic designs