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IBM • Poughkeepsie, Arkansas, United States
Role & seniority: DFT Engineer (mid to senior level; 5+ years required; potential to grow with mentoring responsibilities)
Stack/tools: Synopsys DFT tools (DFT Compiler, TetraMAX, TestMAX, Formality); scan architecture, ATPG, boundary scan, MBIST, IJTAG; Unix/Linux; scripting (Python, TCL, Bash); Makefiles/CI-CD; hardware test flows for ASIC/SoC
Architect and implement DFT strategies for complex SoCs (scan insertion, boundary scan, MBIST, JTAG) and drive DFT methodology improvements
Use Synopsys tools for design testability analysis, test point insertion, fault coverage simulation, and validation
Collaborate with RTL, verification, and physical design; support silicon bring-up, failure analysis, and cross-functional test validation
5+ years hands-on DFT implementation for complex ASIC/SoC in advanced nodes (7nm/5nm or below)
Proven experience with Synopsys DFT tools (DFT Compiler, TetraMAX, TestMAX, Formality)
Deep knowledge of scan, ATPG, boundary scan, MBIST, IJTAG, hierarchical DFT; IEEE1500/IEEE1687; fault models and coverage metrics
Python, TCL, Bash scripting; Unix/Linux; version control (Git)
Experience bringing up silicon and deploying DFT across multiple tape-outs
10+ years in DFT with production test support
Low-power DFT, scan compression, hierarchical DFT
DFT-aware physical design flows (timing closure, floorplanning for test logic)
Makefile-based bui
Introduction
Test Design is a forward-thinking semiconductor team dedicated to delivering testable, high-performance silicon in
innovative ways. We’re looking for a DFT Engineer who values teamwork and brings hands-on experience with
Synopsys tools. If you enjoy solving complex challenges and contributing to a mission-driven engineering culture, you
will be a great fit for our team.
Your Role And Responsibilities
As a Test Design Engineer, you will be responsible for architecting and implementing DFT strategies for complex SoC
designs using Synopsys toolsets. You will collaborate closely with RTL designers, verification engineers, and physical
Developing and integrating DFT architectures including scan insertion, boundary scan, MBIST, and JTAG.
Utilizing Synopsys tools such as DFT Compiler, TetraMax and TestMax for design testability analysis and test point insertion.
Generating test patterns, simulating fault coverage and validating correct circuit behavior and coverage.
Supporting silicon bring-up and failure analysis with test vectors and diagnostics.
Driving DFT methodology improvements and automation for efficiency and scalability.
Collaborating with cross-functional teams to ensure DFT requirements are met throughout the design cycle.
Preferred Education
Master's Degree
Required Technical And Professional Expertise
5+ years of hands-on experience in DFT implementation for complex ASIC/SoC designs in advanced process nodes(e.g., 7nm, 5nm, or below). Proven expertise with Synopsys DFT tools including DFT Compiler, TetraMAX, TestMAX, and Formality. Deep understanding of scan architecture, ATPG, boundary scan, MBIST, IJTAG, and hierarchical DFT methodologies. Demonstrated experience in developing and deploying DFT strategies across multiple tape-outs. Strong scripting skills in Python, TCL, and Bash for automation and tool integration. Solid grasp of IEEE1500, IEEE1687 , fault models (stuck-at, transition, path delay, bridging ) and test coverage metrics. Experience working in Unix/Linux-based environments with large-scale computing and version control systems (e.g., Git).
Preferred Technical And Professional Experience
10+ years of experience in DFT with a track record of successful silicon bring-up and production test support. Experience with low-power DFT techniques, scan compression, and hierarchical DFT Experience with DFT-aware physical design flows, including timing closure and floorplanning for test logic. Proficiency in Makefile-based build systems and CI/CD pipelines for regression and test automation. Experience mentoring junior engineers and leading cross-functional DFT initiatives.