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Vista Applied Solutions Group Inc • Hyderabad, Telangana, India
Role & seniority
Stack / tools
FPGA platforms: Microchip, Xilinx, Altera
Languages: Verilog/SystemVerilog, VHDL, C; testbenches in Verilog/SystemVerilog
EDA / tools: FPGA synthesis, timing closure; on-chip debug tools; lab test equipment
Scripting / repos: TCL, Perl; Git (SVN/GitHub)
Debugging: oscilloscopes, protocol analyzers, Synopsys Identify, Xilinx Chipscope
Top 3 responsibilities
Validate silicon features and perform robust system-level validation for high-speed protocols and embedded subsystems
Develop and execute testbenches, perform hardware board validation, and drive timing closure and performance validation
Lead/mentor on complex FPGA validation efforts (especially for Lead), coordinate project deliverables, and ensure quality across subsystems
Must-have skills
Strong digital fundamentals; hands-on FPGA design and lab validation
Experience with FPGA-based solutions on Microchip/Xilinx/Altera platforms
Proficiency in Verilog/SystemVerilog, VHDL, and C for embedded processors; maintain existing code
Testbench development (Verilog/SystemVerilog), hardware validation on boards, and lab debugging (oscilloscopes, protocol analyzers)
Synthesis, placement/constraints, STA, timing closure for high-speed designs
On-chip debug tools, RTL/C validation, and version control (Git/SVN)
Understanding of hardware architectures, system-level design, and AMB
Hiring for FPGA Silicon Validation Engineer | Onsite | Long Term Contract
Title: FPGA Silicon Validation Engineer (Team Member / Senior / Lead)
Duration: Long Term Contract
Location: Hyderabad, India – 100% Onsite
Process: 2 rounds of interview (Technical Round → Advanced Technical/Panel).
Background Check: Yes
Additional Skills: - Basic knowledge of embedded processors such as ARM Cortex-M3 or RISC-V -Familiarity with AMBA protocols (APB, AHB, AXI, ACE). Embedded software C/C++ programming and bare-metal application development -Board-level debug skills using oscilloscopes, digital analyzers, protocol exercisers, and integrated logic analyzers (e.g., Synopsys Identify, Xilinx Chipscope).
Lead Engineer (SerDes / DDR / SoC / Configuration & Security): - Strong hands-on FPGA silicon validation leadership experience -
Protocol expertise in one or more: PCIe Gen4/5, DDR4/5, Ethernet, Processor-based subsystems - Experience planning and executing complex FPGA system validation projects - Responsible for team-level deliverables and mentoring junior engineers - Deep knowledge depending on domain (SerDes PMA/PCS/DFE/CTLE, DDR interface training and validation, SoC subsystem validation, Configuration/Security including SPI/QSPI/Octal SPI, Crypto, PUF, etc.)
Senior Engineers: - Strong FPGA silicon validation experience -
Hands-on validation in one or more protocols: PCIe Gen4/5, DDR4/5, 100G/50G/40G/25G/10G Ethernet, USB 3.2, JESD204C, 1588 PTP, MIPI, MACSEC - Experience with high-speed memory interfaces (DDR4/5, LPDDR4/5, QDR II+/IV) - Embedded processor and peripheral validation (SPI, I3C, UART, NOC, Trace, USB) - Developing testbenches and validating complex subsystem-level use cases - Strong C programming experience. Validating FPGA configuration and security features Team Members. Hands-on FPGA board-level validation experience. Validation experience in AXI/AHB/APB, SPI, UART, I3C/I2C, USB, SerDes-based protocols, embedded processors, and memory interfaces. Develop validation designs in RTL and C -Validate features at block and subsystem levels