Full Description

Safran est un groupe international de haute technologie opérant dans les domaines de l'aéronautique (propulsion, équipements et intérieurs), de l'espace et de la défense. Sa mission : contribuer durablement à un monde plus sûr, où le transport aérien devient toujours plus respectueux de l'environnement, plus confortable et plus accessible. Implanté sur tous les continents, le Groupe emploie 100 000 collaborateurs pour un chiffre d'affaires de 27,3 milliards d'euros en 2024, et occupe, seul ou en partenariat, des positions de premier plan mondial ou européen sur ses marchés. Safran est la 2ème entreprise du secteur aéronautique et défense du classement « World's Best Companies 2024 » du magazine TIME. Safran Electronics & Defense propose à ses clients des solutions d'intelligence embarquée leur permettant d'appréhender l'environnement, de réduire la charge mentale et de garantir une trajectoire, même en situation critique, ce dans tous les environnements : sur terre, en mer, dans le ciel ou l'espace. La société met les expertises de ses 13 000 collaborateurs au service de ces trois fonctions : observer, décider et guider, pour les marchés civils et militaires.

Descriptif mission

Description of the Role: In this role as a Senior Lead Engineer (FPGA Verification Engineer, Actuation Systems) actively contribute towards Requirement-Based Testing (RBT) in FPGA verification using System Verilog and UVM methodology, in accordance to DO-254 process. Primary Responsibilities: 1.Develop an effective suite of tests and test environments using System Verilog UVM, based tests to achieve predefined requirement verification goals. 2.Develop test-plan, self-checking test-benches to meet the verification criteria and code coverage. 3.Participate in requirement validation and requirement review. 4.Protocols PCIe, SPI, ARINC 429, Mil 1553, Image processing. 5.Actively participate in a team environment and work independently with design teams to develop verification architecture, applications, comprehensive test plans and address issues. 6.Verification environment development from scratch for block level and system level. 7.Work closely with design team on design de-bugging, coverage gap analysis etc. 8.Independently work towards functional and structural coverage closure for module and system level designs. 9.Advanced skills in various programming languages such as System Verilog/UVM, PERL or any scripting language. 10.Apply techniques and skills required to identify a root cause of a given issue and very good debugging skills. 11.Technical guidance to the junior engineers on verification tasks.

Qualifications: Bachelor's/Master's degree in Engineering (ECE or VLSI) 7-11 years of Industry experience with experience in development, integration & verification of ASIC/FPGA. Hands on experience in developing SV-UVM verification environment from scratch. Hands on experience with Questa or Modelsim or similar advanced simulation tools. Hands on experience in DO-254 verification process. Hands on experience in developing UVM verification environment from scratch from scratch with stimulus to achieve the code coverage, robust testing of the designs independently. Exposure to test plan generation, test bench writing, simulation of designs. Experience in RTL Design using VHDL, Complete FPGA development flow and FPGA verification using VHDL will be a plus. Experience in DOORS/Jama will be a plus.Guide Junior engineers in the project execution and take the ownership of the deliverables. Experience in leading team and reporting progress metrics. Excellent oral and written communication skills