Analog/Mixed-Signal Design Verification Engineer
Mediatek • 贺费, Yunnan, China
**Role & seniority: ** AMS (Analog/Mixed-Signal) IP Design Verification; 1+ years ASIC functional verification (hands-on).
**Stack/tools: ** UVM, SystemVerilog/UVM, Verilog, SVA; DV/testbench development, simulation/debug/coverage closure.
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Scripting/automation (plus): Unix/Linux shell, Perl, Python, Makefile, revision control (e.g., Perforce/ClearCase).
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Tech (plus): gate-level simulation, power-aware simulation.
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Top 3 responsibilities:
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Build/extend UVM-based verification environment from spec → test plan → configurable testbench (drivers/checkers) → test suite meeting functional & code coverage goals.
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Develop/support verification components (test cases, drivers, checkers, assertions, reference models) and run RTL + gate-level simulations to achieve coverage closure.
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Support AMS IP/chip DV teams by applying scalable/portable DV capabilities; collaborate globally and improve DV methodology/process for quality/efficiency.
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Must-have skills:
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Strong knowledge of ASIC design flow and UVM DV methodology
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Proficiency in UVM, SystemVerilog/Verilog, and SVA
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Hands-on experience with testbench development, simulation, debugging, coverage closure
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Ability to work from specification to test plan to coverage-driven test suite
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Critical thinking/problem-solving; quick learner
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Nice-to-haves:
- Verification experience with
Full Description
Job Description
Work in AMS IP Design Verification, in UVM-based verification environment. Work in DV process from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions, and reference models, and running RTL and Gate Level simulations and reaching all coverage closures. Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.
Main Requirements and Qualifications
Quick learner with strong critical thinking and creative problem-solving skills. Solid knowledge in ASIC design process, Digital Design and UVM-based design verification methodologies.
Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA). Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc. Knowledge on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals, 1+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal IPs or SERDES IPs, such as USB, UFS, PCIe, DDR-PHY, etc. Power-aware simulations and gate level simulations is a plus
Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., Perforce, ClearCase, etc.) is a plus. Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
Familiar with programming languages: C, C++, and/or SystemC is a plus.
