Design Verification DDR Lead
Mediatek • Bengaluru, Karnataka, India
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Role & seniority
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Verification Engineer (System/Functional Verification), ~5+ years experience
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Focus on HBM4/4e and HBM/DDR IP & subsystem verification
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Stack/tools
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SystemVerilog
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UVM verification methodology
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Simulation & debugging
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Coverage analysis/metrics
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Scripting/automation: Python, Perl, Tcl (or similar)
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Memory interfaces: HBM4/4e, DDR5/DDR4/DDR3
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(Also implies use of industry-standard verification/sim tooling; not explicitly named)
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Top 3 responsibilities
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Develop end-to-end verification plans for HBM4/4e IP/subsystems
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Build/maintain testbenches, test cases, and verification environments in SystemVerilog + UVM
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Execute functional verification (simulation, debug, coverage analysis) and track verification metrics against goals
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Must-have skills
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5+ years verification experience for HBM/DDR IP/subsystems
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Strong RTL/digital design fundamentals and simulation/debug proficiency
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Competency in SystemVerilog + UVM
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Ability to analyze coverage/verification metrics and drive issues to resolution
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Collaboration with design engineers; participation in reviews
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Scripting for automation/tool integration
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Mentoring/technical guidance (lead behavior expected)
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Nice-to-haves
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Experience with other memory protocols
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Broader exposure to additional verification technologies/methodologies
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Full Description
Job Description
Key Responsibilities: 1. Develop and implement comprehensive verification plans for HBM4/4e IP and Subsystem. 2. Create and maintain testbenches, test cases, and verification environments using System verilog and UVM methodology. 3. Perform functional verification of RTL designs, including simulation, debugging, and coverage analysis. 4. Collaborate with design engineers to understand design specifications and requirements for IP and subsystems. 5. Identify and resolve design and verification issues, ensuring high-quality and robust designs. 6. Generate and analyze verification metrics to track progress and ensure coverage goals are met. 7. Participate in design and verification reviews, providing technical expertise and insights. 8. Stay updated with the latest verification technologies and methodologies and apply them to improve verification efficiency and effectiveness. 9. Mentor junior verification engineers and provide technical guidance.
Main Requirements and Qualifications
Qualifications
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Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field.
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5+ years of experience in design verification, with a focus on HBM/DDR (DDR5/DDR4/DDR3) IP or Subsystem verification.
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Knowledge of other memory protocols is a plus.
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Proficiency in verification languages and methodologies, such as System Verilog, UVM, and other industry-standard tools.
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Strong understanding of digital design concepts, RTL coding, and simulation.
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Experience with scripting languages (e.g., Python, Perl, Tcl) for automation and tool integration.
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Excellent problem-solving skills and attention to detail.
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Strong communication and teamwork skills, with the ability to work effectively in a collaborative environment.
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Proven track record of successfully verifying complex IP blocks and subsystems.
