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MTS Digital Verification Engineer

GlobalFoundries Egypt

onsitefull-time
Posted May 11, 2026

**Role & seniority: ** Digital Verification Engineer, senior (10+ years); hands-on leadership for verification strategy, architecture, and signoff quality

**Stack/tools: **

  • Languages/methodology: SystemVerilog, UVM, SVA (Assertions), constrained-random verification

  • Simulation/debug: VCS, Verdi, SpyGlass

  • Automation: Python, Perl, TCL (scripts, regression/infra)

  • Verification flow: regression management, coverage closure (functional/code/assertion)

  • Formal: formal verification tools/methodologies (preferred/optional)

  • Top 3 responsibilities:

    • Own end-to-end verification strategy for IPs and complex SoCs

    • Architect and deploy scalable UVM verification environments

    • Drive verification closure: block/subsystem/full-chip, including coverage closure and efficient debug

  • Must-have skills:

    • Proven SoC-level verification and signoff track record

    • Reusable, scalable verification environment development

    • Strong UVM + SVA skills; constrained-random methodology

    • Simulation expertise with VCS/Verdi/SpyGlass; strong debug ability

    • Deep understanding of clock/reset domain crossing

    • Regression automation experience (CI/CD, dashboards/infrastructure)

    • Scripting for automation (Python/Perl/TCL)

  • Nice-to-haves:

    • Formal verification experience

    • Low-power verification (e.g., **

Full Description

Аbout GlobalFoundries GlobalFoundries (GF) is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GF makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Summery of the Role We are seeking a highly skilled Digital Verification Engineer to lead the verification strategy and execution for complex designs. You will drive methodology, architecture, and signoff quality, working closely with system, digital design, architecture, and physical implementation teams. This is a hands-on leadership role combining deep technical expertise with mentorship and cross-functional influence. Key Responsibilities Define and own end-to-end verification strategy for IPs and complex SoCs Architect and deploy scalable UVM-based verification environments Lead block-level, subsystem, and full-chip verification closure Drive coverage closure (functional + code + assertion) Best practices in: Constrained random verification, Assertions, Regression management and debug efficiently Drives regression automation (CI/CD, regression infrastructure, dashboards) Required skills BS or MS in Electrical and Computer Engineering with 10+ years of experience in digital verification Proven track record in SoC level verification and signoff Experience building reusable and scalable verification environments Proficiency in System verilog, UVM methodology, and Assertions (SVA) Strong experience in simulations and debug tools (e.g. vcs, verdi, spyglass) Deep understanding in clock/reset domain crossing knowledge of scripting (python, perl, TCL) for automation Experience with formal verification tools and methodologies Preferred knowledge in low-power verification (UPF/CPF is a plus) We Offer Base Salary Equity Annual Bonus Plan Medical Insurance Information about our benefits you can find here: https://gf.com/careers/opportunities-in-europe/ We shape what's essential At GlobalFoundries you will find a vibrant work environment where collaboration and innovation thrive. Our diverse and global team shares a culture of respect and inclusivity, representing the best in the industry. We celebrate success together and are united by our dedication to excellence and our desire to improve and empower the world.

Digital VerificationUVMSystemVerilogSVASoC VerificationVCSVerdiSpyglassPythonPerlTCLFormal VerificationUPF/CPFCI/CDConstrained Random VerificationClock/Reset Domain Crossing

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