Full Description

🚀 We Are Hiring | Senior PCIe Design Verification Engineers | Bangalore

Are you passionate about validating next-generation high-speed interconnect technologies and enabling world-class silicon products? Join Silicon Patterns and become part of a team driving cutting-edge semiconductor innovation. We are looking for highly skilled PCIe Design Verification Engineers with strong expertise in PCIe protocol verification across Gen4, Gen5, and Gen6 standards. This is an exciting opportunity to work on advanced SoC and IP verification projects for leading semiconductor customers.

📍 Location: Bangalore

💼 Experience: 5+ Years

⏳ Notice Period: Immediate to 60 Days Preferred

🏭 Domain: Semiconductor | Design Verification

Role Overview As a PCIe Verification Engineer, you will be responsible for architecting and executing comprehensive verification strategies for PCIe-based IPs and subsystems. You will collaborate closely with design, architecture, and validation teams to ensure first-pass silicon success through robust verification methodologies and protocol compliance validation.

Key Responsibilities Develop and maintain advanced verification environments using SystemVerilog and UVM. Verify PCIe Gen4/Gen5/Gen6 Controller, PHY, Endpoint, Root Complex, and Subsystem-level designs. Create reusable verification components, scoreboards, monitors, checkers, and protocol-specific VIP integrations. Design and execute constrained-random and directed test scenarios to achieve functional and code coverage goals. Perform protocol compliance verification, error injection, LTSSM validation, link training, power management, and interrupt verification. Debug complex RTL and verification issues using waveform analysis and simulation tools. Review architecture specifications and develop detailed verification plans and test strategies. Collaborate with design, firmware, and post-silicon teams to identify and resolve functional issues. Drive coverage closure, regression management, and verification sign-off activities. Mentor junior engineers and contribute to verification methodology improvements.

Required Skills & Qualifications

Technical Skills Strong hands-on experience in SystemVerilog and UVM. Extensive experience in PCIe Gen4, Gen5, or Gen6 protocol verification.

Solid understanding of

• LTSSM
• Transaction Layer
• Data Link Layer
• Physical Layer concepts
• Flow Control
• Ordering Rules
• Error Handling & Recovery Mechanisms
• MSI/MSI-X Interrupts
• Power Management States
• Experience with protocol compliance testing and industry-standard PCIe VIPs.

Strong debugging skills using simulation and waveform tools such as

• Synopsys VCS
• Cadence Xcelium
• Siemens Questa
• Verdi
• Experience with coverage-driven verification methodologies.
• Understanding of assertions (SVA), functional coverage, and regression automation.
• Familiarity with scripting languages such as Python, Perl, Shell, or TCL.

Preferred Experience Verification experience on SoC, CPU, AI/ML Accelerator, Networking, Datacenter, or Storage products.

Exposure to high-speed protocols such as

• CXL
• NVMe
• AXI
• Ethernet
• USB
• DDR
• Experience with emulation, FPGA prototyping, or post-silicon validation is an added advantage.

What We're Looking For ✔ Strong protocol expertise in PCIe verification ✔ Excellent debugging and problem-solving abilities ✔ Ability to work independently on complex verification challenges ✔ Strong communication and collaboration skills ✔ Passion for delivering high-quality silicon products

Why Join Us? Work on next-generation semiconductor and high-performance computing technologies. Collaborate with industry-leading experts on challenging verification programs. Opportunity to contribute to advanced PCIe Gen6 and emerging interconnect standards. Dynamic work environment with strong technical growth opportunities.