[HW] SoC Bus Verification Engineer
DEEPX • Mexico City, Ciudad de México, Mexico
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Role & Seniority
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SoC/Bus Verification Engineer (level not explicitly stated; appears mid-to-senior based on verification closure/debug scope)
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Full-time (3-month probation)
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Stack / Tools
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SystemVerilog, UVM (mentions OVM also)
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Arm AMBA protocols: AXI4, ACE, CHI, APB, AHB
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Simulators: VCS, Questa, Xcelium (industry-standard)
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Gate-level simulation: GLS
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Preferred/possible: SVA (formal/property checking), Python/Perl/Tcl
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Top 3 Responsibilities
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Define and execute verification strategy/plans for SoC interconnects and bus structures
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Develop/maintain UVM/SystemVerilog testbenches and achieve verification closure (coverage/debug)
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Verify high-speed bus protocols and validate performance (throughput/latency/arbitration), including post-synthesis GLS
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Must-have Skills
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Strong SystemVerilog + UVM experience
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In-depth knowledge of AMBA AXI/ACE/CHI/ APB/AHB
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Hands-on with VCS/Questa/Xcelium
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Solid understanding of digital logic + SoC architecture
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Ability to debug complex RTL and perform coverage/closure analysis
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Nice-to-haves
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NoC verification experience (e.g., Arteris/Netspeed/Synopsys)
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Scripting (Python/Perl/Tcl) for automation and analysis
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Cache coherency / memory consistency knowledge
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Formal verification (SVA/property checking)
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Interest/experience in NPU/AI accelerator data-flow requirements
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Full Description
Frontier of On-device AI Semiconductors
for Everyone, Everywhere
About DeepX Co., Ltd.
DEEPX is a forward-thinking Series D startup architecting the infrastructure for the Physical AI era.
By delivering the world’s most energy-efficient NPU technology, we are solving the critical power and heat challenges of Generative AI to bring super-intelligence to every device, everywhere.
Our global leadership is validated by our record-breaking recognition as a multi-year CES Innovation Award honoree (2024 & 2026) and being named the 2024 Frost & Sullivan Company of the Year in the NPU sector. With an enterprise value approaching 1 trillion KRW, DEEPX offers a unique pre-IPO
opportunity to join a market leader defining the new industry standard for the $70B AI semiconductor market.
We are currently scaling toward mass production of our flagship DX-M1 (Samsung 5nm) with over 50 global projects scheduled, while engineering next-generation 2nm solutions to support 100B parameter Large Language Models (LLM) at the edge. ☞ Link
★ If you want to be part of world-class innovation? Please talk with us.
★Explore our journey: The DEEPX White Paper ☞ Link
Responsibilities
□ Verification Strategy: Define and develop comprehensive verification plans for complex SoC Interconnects and Bus structures based on architectural specifications.
□ Testbench Development: Build and maintain advanced verification environments using UVM (Universal Verification Methodology) and SystemVerilog.
□ Protocol Validation: Verify high-speed bus protocols (AMBA AXI, CHI, ACE) to ensure data integrity, cache coherency, and protocol compliance.
□ Performance Verification: Analyze bus performance metrics including throughput, latency, and arbitration efficiency to identify and resolve bottlenecks.
□ Debug & Analysis: Conduct deep-dive debugging of complex RTL issues and perform code/functional coverage analysis to achieve 100% verification closure.
□ Gate-Level Simulation: Execute and verify GLS (Gate-Level Simulation) to ensure timing and functional correctness after synthesis.
Qualifications
□ Education: Bachelor’s degree in Electrical/Electronic Engineering, Computer Science, or a related field (Master’s/Ph.D. preferred).
□ Language Proficiency: Strong command of SystemVerilog and experience with UVM/OVM environments.
□ Protocol Expertise: In-depth knowledge of ARM AMBA protocols (AXI4, ACE, CHI, APB, AHB).
□ Verification Tools: Hands-on experience with industry-standard simulators (e.g., VCS, Questa, Xcelium).
□ Logic Design Knowledge: A solid understanding of digital logic design and SoC architecture.
Preferred Qualifications
□ NoC Experience: Experience verifying Network-on-Chip (NoC) IPs (e.g., Arteris, Netspeed, or Synopsys).
□ Scripting Skills: Proficiency in scripting languages such as Python, Perl, or Tcl for automation and result analysis.
□ Coherency Knowledge: Experience with multi-core cache coherency and memory consistency models.
□ Formal Verification: Familiarity with Formal Verification tools and property checking (SVA).
□ AI Hardware Interest: Experience or strong interest in the data-flow requirements of NPU and AI hardware accelerators.
Recruitment Process
□ Application Review - (Phone Interview) - Technical Interview - Organizational Culture Fit Interview - CEO Interview - Reference Check / Compensation Discussion
※ The recruitment process may vary depending on the position and application content.
※ Candidates with less than 3 years of experience are required to submit their academic transcripts.
Employment Type
□ Full-time (3-month probationary period with 100% compensation)
Working Hours
□ Monday to Friday, 9: 00 AM – 6:00 PM (Lunch break: 12:00 PM – 1:00 PM)
Notes
□ If any false information is found in the application or onboarding documents, the job offer may be withdrawn even after confirmation.
□ A 3-month probationary period applies after joining, with no reduction in salary or benefits.
Benefits
□ 모든 정규직 입사자에게 연봉 수준의 스톡옵션 부여
□ 최신 사양 장비 및 최고의 근무 환경 제공 (최신 노트북, 높낮이 조절식 스탠딩 데스크, 모니터암, 듀얼모니터 등 제공)
□ 점심식사 + 아침 & 저녁식사 지원
□ 스낵, 아이스크림, 음료 등 사내 카페 무제한 간식 제공
□ 사우나가 포함된 피트니스 비용 지원
□ 연 1회 종합건강검진 지원 (배우자 포함)
□ 생일, 결혼기념일, 크리스마스이브 축하금 지급 및 조기퇴근 제공
□ 설/추석 명절 상여금 지급
□ 축하와 위로를 위한 경조휴가 및 경조금 지원
