**Role & seniority: ** Staff ASIC Design Verification Engineer (infrastructure custom silicon); leads verification strategy and execution for IP/SoC blocks.

**Stack/tools: **

SystemVerilog, UVM (or OVM) verification methodology
SV assertions; formal and/or emulation exposure
EDA tools + scripting: Python, TCL, Perl, Shell
Top 3 responsibilities:
- Define and execute IP/SoC verification plans; architect UVM-based verification environments and testbenches.
- Develop functional tests, debug failures, and drive coverage closure using verification metrics (test/functional/code).
- Partner cross-functionally (Design, Model, Emulation, post-silicon validation) to enable first-pass silicon success.
Must-have skills:
- 8+ yrs hands-on verification experience with SystemVerilog/UVM and/or C/C++-based verification
- Proven experience in IP/subsystem/SoC-level verification (SV UVM/OVM)
- Verification infrastructure architecture and ability to execute full verification cycle
- EDA tools + scripting to build verification flows
- Familiarity with power management verification concepts
Nice-to-haves:
- Verification of compute/memory/interconnect for AI/ML accelerator or data center networking SoCs
- Experience with ARM/RISC-V/GPU subsystem verification
- Familiarity with host/system software stacks affecting hardware

Full Description

Meta's Infrastructure Silicon team is seeking a Staff ASIC Design Verification Engineer to lead verification strategy and execution for custom silicon powering Meta's data center infrastructure. In this role, you will architect and drive end-to-end verification of complex IP blocks and SoCs designed for AI/ML acceleration, networking, and storage workloads. You will define scalable UVM-based verification environments, establish coverage closure methodologies, and partner with design, emulation, and post-silicon validation teams to ensure first-pass silicon success across Meta's infrastructure ASIC portfolio.

Responsibilities

Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on the verification test plan Drive design verification to closure based on defined verification metrics on the test plan, functional, and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the design team Collaborate with cross-functional teams like Design, Model, Emulation, and silicon validation teams towards ensuring the highest design quality Develop and drive continuous design verification improvements using the latest verification methodologies, tools, and technologies from the industry

Minimum Qualifications

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience 8+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification 8+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in one or more of the following areas, along with functional verification, SV assertions, formal, and emulation Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience in architecting and implementing design verification infrastructure and executing the full verification cycle Familiarity with power management verification concepts

Preferred Qualifications

Experience verifying compute, memory, or interconnect subsystems within AI/ML accelerator or data center networking SoCs Experience with ARM, RISC-V, or GPU-based subsystem verification at the IP or full-chip level Familiarity with host and system-level software stacks as they relate to hardware functional verification and stimulus generation Experience with chiplet-based architectures and package-level integration verification methodologies

$178,000/year to $250,000/year + bonus + equity + benefits

ASIC Engineer, Power Management Design Verification

Full Description