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LanceSoft, Inc. • Longmont, Colorado, United States
Salary: USD 60–70 per hour
Role & seniority
Stack / tools
SystemVerilog RTL and UVM-based verification
Industry simulators: Synopsys VCS, Cadence Xcelium, QuestaSim, ModelSim
PCIe, DMA, CXL, VIP models (Siemens/Cadence/Synopsys)
Verilog/SystemVerilog, IP verification, possibly Vivado and FPGA-related tools (nice-to-have)
Scripting: Python, Bash, Perl, TCL (nice-to-have)
Linux exposure (nice-to-have)
Top 3 responsibilities
Design and verify block(s) of IP; develop and improve simulation test environments (directed and constrained-random tests)
Collaborate with design/verification team to understand functionality within block/system; adapt verification methodologies
Conduct PCIe device verification tasks (DMA, CXL, IDE, VIP models, traffic generators/checkers) and support chip bring-up/test
Must-have skills
Fluent in synthesizable SystemVerilog; able to design basic modules
Class-based verification with SystemVerilog; UVM strongly preferred
Proficient in simulation/debug using VCS, QuestaSim, or Xcelium
Strong understanding of ASIC/FPGA concepts; RTL verification experience
Strong debugging, analytical skills; excellent written and verbal communication
3+ years verification experience on Verilog/SystemVerilog; familiarity with PCIe; good grasp of verification methodologies
Nice-to-have
FPGA experience (Xilinx) and Vivado
Experience with licensed VIP from Siemens/Cadence/Synopsys
ASIC/FPGA bring-up af
Pay Rate: $60.00/hr to $70.00/hr on W2
Location: Longmont, CO (100% onsite) - open to hybrid option after a trial period.
Interviews: Onsite Interview with team members
Must be fluent in the synthesizable constructs of SystemVerilog; should be able to design a basic module without any trouble
Must be competent in class-based verification techniques using SystemVerilog; UVM experience is highly preferred, but other frameworks like VMM, OVM, or something custom are still valuable
Must be familiar with how to compile and run a simulation, open a design, and debug it using an industry standard simulator like Synopsys’ VCS, Siemens QuestaSim, or Cadence Xcelium
Must have a good understanding of the industry landscape; should understand and articulate ASIC and FPGA-relevant concepts
Must be able to pick up new techniques quickly and be a strong self-learner; candidate should be able to design new features thoughtfully after considering all tradeoffs with guidance from senior engineers
Nice-to-have skills: FPGA Experience (Xilinx/FPGA preferred), Vivado experience
Write scripts quickly for task automation or result summaries: Python, Bash, Perl, TCL, etc.
High speed IO familiarity like Ethernet, PCIe, CXL
Design creation with Vivado toolchain; familiarity with various IPs
Linux kernel debugging experience
Experience with licensed verification IP (VIP) from Siemens, Cadence, or Synopsys
ASIC or FPGA bring-up after chip tapeout
In this role you will be part of a PCIe development and productization team. A majority of the verification will target PCIe device testing DMA, CXL, IDE, VIP models, traffic generators/checkers, etc.
3 or more years of proven verification experience on Verilog and System Verilog for IP development and verification required
Familiar with UVM verification methodologies and environments
Strong debug skills
Experience with simulation tools ModelSim/VCS and VIPs
Experience in Verilog/SystemVerilog
Strong analytical skills and attention to detail
Excellent written and communication skills
Familiarity with PCIe and serial protocols is a bonus
FPGA and tools experience is a bonus
Essential skills: RTL verification experience, Verilog/System Verilog, Modelsim/VCS, UVM
Nice-to-have skills: FPGA Experience (FPGA preferred), Vivado experience