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ASIC Engineer, Design Verification

Meta Bengaluru, Karnataka, India

onsite
Posted Aug 17, 2026

**Role & seniority: ** Infra Silicon – ASIC/SoC Design Verification Engineer (entry-level/early-career; requires degree in progress/complete prior to joining)

**Stack/tools: **

  • HDL/DV: SystemVerilog, C/C++ verification

  • Verification methodology: constrained-random, coverage-driven; functional/code coverage closure

  • Debug: Verdi or equivalent

  • EDA/workflows: EDA tools + scripting Python/TCL/Perl/Shell to build verification flows

  • DV frameworks: standard DV techniques; UVM (preferred)

  • Revision control: Git/Hg/SVN (preferred)

  • Top 3 responsibilities:

    • Develop functional tests from the verification test plan

    • Drive verification to closure against defined metrics (functional + code coverage)

    • Debug, root-cause, and resolve functional failures with design/arch teams; coordinate cross-functional closure

  • Must-have skills:

    • Constrained-random, coverage-driven verification experience

    • Verifying an IP block using standard DV techniques

    • EDA tool fluency and scripting for verification environments (Python/TCL/Perl/Shell)

    • Understanding of at least one domain: computer architecture / CPU / GPU / networking / interconnects / fabrics

    • BS (or in-progress, completed prior to joining) in relevant technical field

  • Nice-to-haves:

    • MS in relevant field

    • Line-of-RTL debugging and bug-fix closure using Verdi/equivalents

    • Building SystemVerilog/UVM veri

Full Description

The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing proficiency with increased capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains.

Responsibilities

Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the design/arch team Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality meets defined verification criteria

Minimum Qualifications

Currently has, or is in the process of obtaining a Bachelor's degree in Electronics Engineering, Computer Engineering, Computer Science, Very Large Scale Integration (VLSI), relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta Experience using constrained-random, coverage driven verification or C/C++ verification Experience in verifying a IP block using standard Design Verification (DV) based techniques Experience in Electronic Design Automation (EDA) tools and scripting (Python, Tool Command Language (TCL), Perl, Shell) used to build tools and flows for verification environments

Understanding in at least one of the following areas: computer architecture, Central Processing Unit (CPU), Graphics Processing Unit (GPU), networking, interconnects, fabrics or similar designs

Preferred Qualifications

Currently has, or is in the process of obtaining, a Master’s degree in Electronics Engineering, Computer Engineering, Computer Science or similar technical field Experience debugging fails to the line of RTL, closing out bug fixes, using Verdi or equivalent debug tools Experience in development of SystemVerilog/UVM based verification environments from scratch Experience in verification of any peripheral IPs like UART, SPI, I2C and exposure to protocols like APB, AXI Experience with revision control systems like Mercurial(Hg), Git or SVN Experience working in a CPU/GPU environment

ASIC Design VerificationSystemVerilogUVMC++PythonTCLPerlShell ScriptingEDA ToolsRTL DebuggingConstrained-random VerificationCoverage Driven VerificationComputer ArchitectureSoC VerificationProtocol VerificationHardware Accelerationmulti-location

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