Senior MXS Verification engineer
Retym • Austin, Texas, United States
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Role & seniority
- Sr. Mixed-Signal Verification Engineer
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Stack/tools
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Verification/HDL: SystemVerilog, Verilog, UVM
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AMS verification: AMS tools for behavioural-model validation (with BM validation)
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Analog design tooling: Virtuoso Schematics (Cadence)
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EDA (preferred): Synopsys and Cadence tool experience
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Simulation workflow: simulators, waveform viewers, execution automation, coverage collection
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Top 3 responsibilities
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Develop mixed-signal verification strategies and UVM-based testbenches from specifications.
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Create behavioural models (BM) for analog blocks to support digital verification.
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Run, debug, and troubleshoot unit/cluster/top-level mixed-signal simulations; validate BM correctness using AMS tools.
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Must-have skills
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10+ years verification experience
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Analog behavioural modelling for digital verification
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Mixed-signal dynamic verification with chip digital tools (explicitly noted: “no AMS”)
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Strong SystemVerilog/Verilog coding
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Basic analog design knowledge
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Virtuoso Schematics tool familiarity
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Nice-to-haves
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UVM experience
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Experience with both Synopsys and Cadence tools
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Familiarity with scalable/portable test case development
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Strong ability to write test plans and communicate results
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Location & work type
- Not specified in provided text.
Full Description
For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Sr Mixed signal verification engineer.
Requirements
Key Responsibilities
- Develop verification strategies for digital and analog (mixed-signal) designs, utilizing UVM methodologies based on specifications.
- Create behavioural models for analog blocks in accordance with guidelines provided by analog designers.
- Write, execute, and debug testbenches using UVM methodology and SystemVerilog code for mixed-signal blocks.
- Run and debug behavioural model (BM) validation using AMS tools to ensure the correctness of the behavioural models.
- Perform and troubleshoot unit-level, cluster-level and top-level simulations of mixed-signal designs.
- Minimum Qualifications
- 10+ years of experience
- Experience in Behavioural Modelling (BM) of Analog design for digital verification
- Knowledge in Mixed Signals dynamic Verification using chip digital design tools [no AMS]
- Experience in Verilog/SystemVerilog coding
- Experience in Virtuoso Schematics tools
- Basic knowledge in Analog design
- Preferred Qualifications
- Experience in UVM
- Experience in both Synopsys and Cadence tools is an advantage
- Additional Skills
Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases.
Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment.
Communication: Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams.
