Senior Design Verification Engineer
Baya Systems • Cambridge, England, United Kingdom
**Role & seniority: ** Senior Hardware Verification Engineer (8+ years), hands-on Design Verification
**Location & work type: ** Cambridge, England, UK; hybrid possible within the UK
**Stack/tools: **
-
Languages: Verilog, SystemVerilog
-
Verification framework: UVM
-
APIs/Protocols: ARM AXI, APB, AHB; ARM CHI (nice-to-have)
-
Automation: Python (modern programming language)
-
EDA tooling: Industry-standard simulation/debug tools (unspecified)
-
(Bonus) formal verification/emulation platforms (unspecified)
-
Top 3 responsibilities:
-
Create test plans for highly configurable IPs (SoC/chiplet/multi-chiplet interconnectivity)
-
Implement testbenches, checkers, and scoreboards using UVM/SystemVerilog
-
Collaborate across teams (design/DV/software) to define configurable testbenches, debug failures, and close coverage
-
-
Must-have skills:
-
Block-level/IP-level/SOC-level verification experience; currently hands-on
-
Strong UVM-based verification expertise (test sequences, verification components)
-
Proficiency in Verilog/SystemVerilog
-
AXI/APB/AHB understanding
-
Debugging, coverage closure, and strong communication/collaboration
-
-
Nice-to-haves:
-
ARM CHI protocol knowledge
-
Experience with caches, cache coherency, memory subsystems, interconnects, and NOCs
-
Formal verification and/or emulation experience
-
Python usage for verification workflows
-
-
**E
Full Description
Job Title: Senior Hardware Verification Engineer
Location: Cambridge, England, United Kingdom (Hybrid possible inside the UK)
About the Role: We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions
Responsibilities
- Collaborate with design and architecture teams to create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or multi chiplet systems
- Write UVM/SystemVerilog code to implement the test plan, checkers and scoreboards
- Collaborate with software teams to define and implement configurable testbenches
- Work with design and DV engineers to implement the test plan, debug failures, close coverage, etc.
Qualifications
- BS/MS in Electrical Engineering, Computer Engineering or Computer Science
- 8+ years and current hands-on experience in block-level/IP-level/SOC-level verification
- Proficiency in Verilog, SystemVerilog
- Familiarity with industry-standard EDA tools for simulation and debug
- Deep experience with UVM-based testbenches
- Experience with modern programming languages like Python
- Knowledge of ARM AMBA protocols such as AXI, APB, and AHB
- Understanding of ARM CHI protocol is a plus
- Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NOCs
- Experience with formal verification techniques, emulation platforms is a plus
- Excellent problem-solving skills and attention to detail
- Strong communication and collaboration skills
