Hardware - Senior Design Verification Engineer
FuriosaAI • Seoul, South Korea
**Role & seniority: ** Design Verification Engineer (block/system level); 5+ years experience (mid-senior)
**Stack/tools: **
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SystemVerilog + UVM (block/system verification)
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EDA tools (verification workflows)
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Scripting: Python, Perl, Shell
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Verification infrastructure: planning → execution → closure
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Preferred: cocotb (Python), high-speed interface verification (e.g., PCIe, UCIe, UALink, Ethernet)
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Top 3 responsibilities:
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Define and implement block/system-level verification strategies and metrics
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Create test plans and develop test harnesses/sequences; ensure functional & code coverage
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Drive verification closure and partner with Design/Emulation/Silicon Validation to debug and root-cause functional failures
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Must-have skills:
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SystemVerilog/UVM-based verification experience (block + system level)
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EDA tool proficiency
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Scripting ability to build verification tools/flows (Python/Perl/Shell)
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Ability to architect and run the full verification cycle to closure
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Nice-to-haves:
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Master’s degree
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Advanced UVM environment development
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Python-based verification (e.g., cocotb)
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IP/integration verification for high-speed interfaces (PCIe/UCIe/UALink/Ethernet)
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SoC/subsystem verification for ARM/RISC-V
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Strong Python and communication skills
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Location & work type: Global company with offices in *Korea
Full Description
About FuriosaAI FuriosaAI builds high-performance, high-efficiency AI compute for the Inference Era. Founded in 2017 by veteran semiconductor and AI algorithm engineers, Furiosa operates globally with offices in Korea and Silicon Valley, along with a compiler-focused R&D lab in Lisbon. Our vision is to make AI computing sustainable, enabling access to powerful AI for everyone on Earth. We solve the AI hardware energy and operational cost crisis at the architectural level, rather than through brute force, building the world's first truly AI-native compute platform to unlock the full potential of artificial intelligence for every enterprise.
Key Responsibilities Define, plan, and implement block and system level verification strategies Write and review test plans, develop test harnesses and test sequences Drive the design verification process to successful closure by meeting defined verification metrics across the test plan, functional coverage, and code coverage Collaborate closely with the Design team to debug, root-cause, and resolve functional failures within the design Work collaboratively with cross-functional teams, including Design, Model, Emulation, and Silicon Validation, to ensure the highest standards of design quality
Basic Qualifications Bachelor's degree in Electrical Engineering, Computer Science, or a closely related technical field 5+ years of experience in block and system level verification utilizing SystemVerilog/UVM-based methodologies Proven experience with Electronic Design Automation (EDA) tools and proficiency in scripting languages (Python, Perl, Shell) for developing verification tools and flows Experience in architecting and deploying Design Verification infrastructure, including executing the complete verification cycle from planning to closure
Preferred Qualifications Master’s degree in Electrical Engineering, Computer Science, or a closely related technical field Expertise in developing UVM-based verification environments from initial setup Expertise in developing Python-based verification environment such as cocotb Experience in IP or integration verification for high-speed interfaces such as PCIe, UCIe, UALink, and Ethernet Experience verifying ARM/RISC-V-based sub-systems or SoCs Strong Python programming skills Excellent written and verbal communication skills
Contact recruit@furiosa.ai
